Synthesis of Integer in Verilog

[ash72]

Hello,

I understand that it's not a good idea to use integers in RTL that is to be synthesized. In the following code, it will generate 32 bit incrementor. But my question is on the continuous assignment.

integer I;
always @(posedge Clock)
if ( Reset || (I == 255) )
I <= 0;
else I <= I + 1; //32-bit incrementor

wire [7:0] Count = I;

Will the wire assignment generate an eight bit counter? Or will it simply synthesize into an 8 bit bus.
Thanks.

 

[FvM]

I is synthesized as 8 bit variable because the value doesn't exceed 255. The wire assignment doesn't matter.

 

[barry]

I never heard that rule. The synthesis tools are generally smart enough to figure out the best implementation (it will throw away unused bits.)

 

[ads-ee]

Verilog truncates or zero fills assignments. So having a continuous assignment of Count = I; will force I to be 8-bits by dropping all the bits from 8 and up.

I wouldn't matter if "I" was supposed to count from 0-1023 it would still end up as being an 8-bit assignment. All you will see is a synthesis warning telling you there is a assignment of a 32-bit (typical integer bit width) to an 8-bit and that the upper bits will be truncated.

 

[jdb2]

Hello,

I understand that it's not a good idea to use integers in RTL that is to be synthesized. In the following code, it will generate 32 bit incrementor. But my question is on the continuous assignment.

integer I;
always @(posedge Clock)
if ( Reset || (I == 255) )
I <= 0;
else I <= I + 1; //32-bit incrementor

wire [7:0] Count = I;

Will the wire assignment generate an eight bit counter? Or will it simply synthesize into an 8 bit bus.
Thanks.

There are several problems with your code. First, you're using the integer type, which isn't always synthesizable -- you should use a reg type or logic type ( as it appears you code is SystemVerilog from the implicit continuous assignment ) for the counter variable ( Also, the "integer" data type is a 2-state type which might not be desirable ). Second, you have your count limit detection code mixed in with your synchronous reset code which could cause problems with synthesis. Lastly, due to your code resetting the count when it reaches 255, you're actually modelling an 8-bit incrementor, not a 32-bit incrementor and besides that, you're assigning the integer's value to an 8-bit net which will truncate the value in the integer "I" variable. Here is the corrected SystemVerilog code :

---

Code Verilog - [expand]
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var logic [31:0] I; //The "var" isn't really needed because the SystemVerilog
                           //EDA tool you're using will normally take a "logic" type assigned
                           //to from a procedural block to be a variable -- I just wanted to make it
                           //clear that it's indeed a variable.
always_ff @(posedge Clock)
begin
        if (Reset) I <= '0;
        else if (I == ($pow(2, 32) - 1)) I <= 0;
        else I <= I + 1;
end
 
logic [31:0] Count = I;

---

Hope this helps,

jdb2

 

[FvM]

By omitting "(I == 255)" you are changing the effective variable width from 8 to 32 bit. Why?

 

[barry]

There are several problems with your code. First, you're using the integer type, which isn't always synthesizable -- you should use a reg type or logic type ( as it appears you code is SystemVerilog from the implicit continuous assignment ) for the counter variable ( Also, the "integer" data type is a 2-state type which might not be desirable ). Second, you have your count limit detection code mixed in with your synchronous reset code which could cause problems with synthesis. Lastly, due to your code resetting the count when it reaches 255, you're actually modelling an 8-bit incrementor, not a 32-bit incrementor and besides that, you're assigning the integer's value to an 8-bit net which will truncate the value in the integer "I" variable. Here is the corrected SystemVerilog code :

---

Code Verilog - [expand]
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var logic [31:0] I; //The "var" isn't really needed because the SystemVerilog
                           //EDA tool you're using will normally take a "logic" type assigned
                           //to from a procedural block to be a variable -- I just wanted to make it
                           //clear that it's indeed a variable.
always_ff @(posedge Clock)
begin
        if (Reset) I <= '0;
        else if (I == ($pow(2, 32) - 1)) I <= 0;
        else I <= I + 1;
end
 
logic [31:0] Count = I;

---

Hope this helps,

jdb2

Since when aren't integers synthesizable?

 

[jdb2]

Since when aren't integers synthesizable?

I didn't say they aren't synthezisable; I said they "might" not be synthesizeable. I've never had many occasions to use Verilog integers for synthesis -- I use them mainly for eg. for loop variables to generate code. I thought I remember having problems with Verilog integers with regard to synthesizing them a long while ago ( years ), but as far as I can tell according the the IEEE Verilog synthesizeable subset document, they are synthesizable -- I apologize for any confusion.

Regards,

jdb2

 

[jdb2]

By omitting "(I == 255)" you are changing the effective variable width from 8 to 32 bit. Why?

I thought the OP wanted a 32-bit counter. His original code was using a 32-bit integer but limiting its range to 0 through 255. Perhaps I mistook the OP's intentions?

Regards,

jdb2

 

[jdb2]

( Also, the "integer" data type is a 2-state type which might not be desirable ).

This is actually not true -- Verilog integers are 4-state types. It seems I got "integer" mixed up with SystemVerilog's 2-state "int" type.

jdb2