synthesis of a design having clock domain crossing CDC paths

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tariq786

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Hi

I want to know how would you synthesize a design having multilple clock domains with clock domain crossing paths between the two clock domains.

What would be the constraints for CDC paths?

How would you verify the result of synthesis


Please reply thoroughly.

Thanks a lot
 

You need to use a create_clock for each valid clock input, check if there are some remaining clock pins not connected to define clock net.
In general, you need to define false path from one clock domain to other one clock domain.
RC (Cadence), apply this false path automatically if you used the -domain <unique_name> argument in create_clock command.
 
On the synchronizers, should a multi-cycle constrain be applied (beside the false path)?
 
The answer is "No"
 
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