How should be handled black boxes in the RTL during the synthesis? Let's say I have a Black Box in my Netlist, which represents an analog module. There are requirements on the timing for its inputs and outputs. How should I implement this timing in the synthesis/sta scripts? Again, this block box is inside another code and does not have its own ports in the top-level.
The easiest way is to create (manually or by using special software) the timing model of such block with all needed requirements. Timing model - it's a synopsys .linb file (as example). Special software - it's a characterization tool (Synopsys Liberty NCX) (it may be difficult to run it on the analog block).
Then, you may use this timing model (.lib) in the same manner as you are using other .lib files (of std. cells). In DesignCompiler you should add this .lib in the link_library.