synthesis for gated clock and muxed clock

[qjlsy]

For a gated clock design, what special DC constraints need to be added?

And how about those for a muxed clock design?

Thanks a lot!

 

[eda_wiz]

set_clock_gating_style -positive_edge_logic {integrated:TLATNCAX1} -max_fanout 5
set_clock_gating_signals -design design_name
elaborate design_name -gate_clock
report_clock_gating -gated -ungated -hier -verbose -gating_elements >report

For Muxed Clock use set_disable_timing.
or set_case analysis while STA

regards

 

[ivlsi]

could someone please explain what's doing each of the command in the previous post?

- - - Updated - - -

why a max fanout should be defined for the gating style?
should not the clock gating signals be listed explicitly?
why gating on positive_edge_logic? does it mean that gate be inserted for the falling edge?

 

[dftrtl]

set_clock_gating_style -positive_edge_logic -max_fanout 5 --> Tells we are trying to gate clock low: Fanout is mentioned not to load
set_clock_gating_signals -design design_name --> Mentioning the hierarchy
elaborate design_name -gate_clock --> Elaborating design with gating enabled
report_clock_gating -gated -ungated -hier -verbose -gating_elements > report --> Generate Report