Synthesis constraints - confused about period constraints

[tariq786]

Synthesis Constraints

I am slightly confused about period constraints?
I am in the design exploration phase. I don't know what is the highest clock frequency my design can work with.

How do i quickly find out such details in the FPGA design flow? And once i find out such details, do i have to write constraint file?

Please help precisely

 

[nareshgtr]

Re: Synthesis Constraints

You need not write constrain file. Use GUI for frequency setting in tool. Set the required frequency verify all timings(setup, hold time). For maximum operating frquency keep increasing the frequency step-by-step, until you find negative slack.
Regards
V. Naresh Kumar