Synthesis clock frequency

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Anuvesh

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hi friends,

At the time of synthesis, if i am given any clock constraint in SDC then it is synthesisable or not ??

if synthesis is done which clock frequency it ll consider ??


please can any one clear my doubt.
 

It will just transform the rtl into gate, without trying to reach any timing constraint.
This usage is mainly to check the rtl code.
 

sorry,, if i don't have any clock constraint in my SDC then what happens???

what frequency it ll consider at the time of synthesis STA..??
 

As there is no constraint defined in the tool to synthesize ,it will not synthesize for best frequency..chk the synthesize report I think it will give the max operating frequency..
 

chk your report,somewhere it will be mentioned,...Since there is no Constantin tool will not synthesize for best frequency.
 

unless until u give some constraint to any toll, it will not synthesize for better condition and it will choose easiest paths to complete tasks..
 
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