samiksha
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I'm designing a structure in VHDL with clock. the design is getting simulated and giving me the correct output but when i synthesise that code, i get the following information regarding delay.
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: No path found
And also the area result does not show any LUT utilization?
Can anyone let me know the problem in the design?
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: No path found
And also the area result does not show any LUT utilization?
Can anyone let me know the problem in the design?