Syntax question: using WHEN statements

[neocool]

Hi, how do I implement something like that in one line, so that I don't drive DOUT at two locations?

DOUT <= DO_higher(SAMPLE_WIDTH-1 downto 0) when (CSN='0' and RDN='0' and ADDR(8)='1');
DOUT <= DO_lower(SAMPLE_WIDTH-1 downto 0) when (CSN='0' and RDN='0' and ADDR(8)='0');

Thanks

 

[khorram]

One of solutions is as follows:
DOUT <= DO_higher(SAMPLE_WIDTH-1 downto 0) WHEN CSN='0' and RDN='0' and ADDR()='1' ELSE DO_lower(SAMPLE_WIDTH-1 downto 0) WHEN CSN='0' and RDN='0' and ADDR()='0' ELSE DEFAULT_VALUE;

ANOTHER WAY:
Why don't you use an IF statement in a PROCESS statement instead of them?

You can replace them by the following process statement:

process(CSN, RDN, ADDR, DO_higher, DO_lower)
begin
if (CSN='0' and RDN='0' and ADDR()='1') then
DOUT <= DO_higher(SAMPLE_WIDTH-1 downto 0);
elsif (CSN='0' and RDN='0' and ADDR()='0') then
DOUT <= DO_lower(SAMPLE_WIDTH-1 downto 0);
else
DOUT <= DEFAULT_VALUE;
end if;
end process;

Regards,
KH

 

[neocool]

So, it's allowed to use when-else-when-else statement..
I've tried it before, but I guess I've made some other mistake, so it didn't compile.

The reason I wanted to avoid process and if statements is because ISE adds a latch at the output, so there is a delay of one clock. I wanted to create no delay as this is a small fix inside my design.
Is there a way to remove that latch and still use IF inside process?

Regards

 

[khorram]

If you have an incomplete if statement, the synthesis tool will generate a latch. As you can see in the code, last else statement prevents to make a latch. You should assign a default value to the DOUT.

process(CSN, RDN, ADDR, DO_higher, DO_lower)
begin
if (CSN='0' and RDN='0' and ADDR()='1') then
DOUT <= DO_higher(SAMPLE_WIDTH-1 downto 0);
elsif (CSN='0' and RDN='0' and ADDR()='0') then
DOUT <= DO_lower(SAMPLE_WIDTH-1 downto 0);
else
DOUT <= DEFAULT_VALUE;
end if;
end process;

Regards,
KH