LibraryIEEE;useIEEE.std_logic_1164.all;useIEEE.std_logic_arith.all;useIEEE.std_logic_unsigned.all;entity AC isPort( store :inSTD_LOGIC;
ld_AC :inSTD_LOGIC;
RAZ :inSTD_LOGIC;
clk :inSTD_LOGIC;
D :inSTD_LOGIC_VECTOR(15downto0);
Q :outSTD_LOGIC_VECTOR(15downto0);
Q_mem :outSTD_LOGIC_VECTOR(15downto0));end AC;architecture Behavioral of AC issignal temp:STD_LOGIC_VECTOR(15downto0);beginprocess(RAZ,clk)beginif RAZ = '0' then
Q <=(Q'range=> '0');elsif(clk='1' and clk'event)thenif(ld_AC ='1')then
temp <= D;elseif(store='1')then
Q <= temp;else Q <="ZZZZZZZZZZZZZZZZ";endif;endif;endprocess;end Behavioral;
I have an error "syntax error near process". Can anybody help me ? I think I forgot an "end if" but i'm note sure.
i am surprised that it is you who is telling such sweet things!!!...you never gave me any freebies when I was a fresher ...i do not know if you do remember them...btw I dont consider it vague because "else if" is a basic error and the compiler would definitely show where the person what is wrong...i am just telling the op to go through the basic syntaxes and its the way to go about...else if are the commands you use in software based compilers....these are the errors which should be avoided...
as far as i am concerned it looked like a vhdl code because verilog has a much different syntax as compared to vhdl and i believe i have read that its more flexible than vhdl like a software code but of course has its own drawbacks as compared to vhdl...
well there are more bad responses at xilinx user forums for a silly typing error...i am sure you are aware of it...
Yes, you can tristate an output, creating a tristate driver, and it can well serve a purpose. Consider e.g. the data port of a bus connected ROM, or simply an open drain output.
Regarding the "else if" syntax error, it can be legal VHDL syntax, but needs another closing end if. You can see elsif just as a shortcut.
Code:
if condition_a then
--
else if condition_b then
--
end if;
end if;