syntax error near process

[bob2987]

Hi All !

I'm a student in VHDL design and I am trying to create an accumulator in VHDL. This is my code :

---

Code VHDL - [expand]
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Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
 
entity AC is
    Port ( store : in STD_LOGIC;
           ld_AC : in STD_LOGIC;
           RAZ : in STD_LOGIC;
           clk : in STD_LOGIC;
           D : in STD_LOGIC_VECTOR (15 downto 0);
           Q : out STD_LOGIC_VECTOR (15 downto 0);
           Q_mem : out STD_LOGIC_VECTOR (15 downto 0));
end AC;
 
architecture Behavioral of AC is
signal temp: STD_LOGIC_VECTOR (15 downto 0);
 
begin
 
process (RAZ,clk)
 
begin
 
if RAZ = '0' then
Q <= (Q'range => '0');
 
elsif (clk='1' and clk'event) then
        if (ld_AC ='1') then
        temp <= D;
        else if (store='1') then
        Q <= temp;
        else Q <= "ZZZZZZZZZZZZZZZZ";
        end if;
end if;
 
end process;
 
end Behavioral;

---

I have an error "syntax error near process". Can anybody help me ? I think I forgot an "end if" but i'm note sure.

Thank you.

Bob

 

[imbichie]

make this else if (store='1') then like this elsif (store='1') then

 

[sreevenkjan]

you cannot use software syntaxes in your vhdl code.you need to use the vhdl syntaxes.

 

[TrickyDicky]

you cannot use software syntaxes in your vhdl code.you need to use the vhdl syntaxes.

what software syntax are you referring to? The op just made a simple error as imbichi pointed out.

its much easier for the op if you actually help, rather than just make some vague comments

 

[sreevenkjan]

what software syntax are you referring to? The op just made a simple error as imbichi pointed out.

its much easier for the op if you actually help, rather than just make some vague comments

i am surprised that it is you who is telling such sweet things!!!...you never gave me any freebies when I was a fresher ...i do not know if you do remember them...btw I dont consider it vague because "else if" is a basic error and the compiler would definitely show where the person what is wrong...i am just telling the op to go through the basic syntaxes and its the way to go about...else if are the commands you use in software based compilers....these are the errors which should be avoided...

 

[TrickyDicky]

Else if is used in verilog, and that is a hardware language.

The op made a simple typing error. Otherwise the code is good. Its hardly written like software.

- - - Updated - - -

On a design, rather than code point, you cannot tri state an output ( well you can, but there's no point.)

 

[sreevenkjan]

as far as i am concerned it looked like a vhdl code because verilog has a much different syntax as compared to vhdl and i believe i have read that its more flexible than vhdl like a software code but of course has its own drawbacks as compared to vhdl...

well there are more bad responses at xilinx user forums for a silly typing error...i am sure you are aware of it...

 

[FvM]

On a design, rather than code point, you cannot tri state an output ( well you can, but there's no point.)

Yes, you can tristate an output, creating a tristate driver, and it can well serve a purpose. Consider e.g. the data port of a bus connected ROM, or simply an open drain output.

Regarding the "else if" syntax error, it can be legal VHDL syntax, but needs another closing end if. You can see elsif just as a shortcut.

if condition_a then
--
else if condition_b then
--
  end if;
end if;