[SOLVED] Syntax error in VHDL program

Can anyone tell me whats wrong with this program??

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity top is
port
(
clk_in : in std_logic;
reset : in std_logic;
WEN : in std_logic; -- taken as active high
REN : in std_logic; -- taken as active high
WADDR : in std_logic_vector(11 downto 0);
RADDR : in std_logic_vector(11 downto 0);
ram_dout : out std_logic_vector(2 downto 0);
)
end top;

architecture rtl of top is

component VCC
port( Y : out std_logic);
end component;

component GND
port( Y : out std_logic);
end component;

component counter
port
(
clk : in std_logic;
reset : in std_logic;
sel : in std_logic;
qa : out std_logic_vector(2 downto 0);
qb : out std_logic_vector(2 downto 0)
);
end component;

component RAM4K9
generic (MEMORYFILE:string := "");
port
(
ADDRA11, ADDRA10, ADDRA9, ADDRA8, ADDRA7, ADDRA6,
ADDRA5, ADDRA4, ADDRA3, ADDRA2, ADDRA1, ADDRA0, ADDRB11,
ADDRB10, ADDRB9, ADDRB8, ADDRB7, ADDRB6, ADDRB5, ADDRB4,
ADDRB3, ADDRB2, ADDRB1, ADDRB0, DINA8, DINA7, DINA6,
DINA5, DINA4, DINA3, DINA2, DINA1, DINA0, DINB8, DINB7,
DINB6, DINB5, DINB4, DINB3, DINB2, DINB1, DINB0, WIDTHA0,
WIDTHA1, WIDTHB0, WIDTHB1, PIPEA, PIPEB, WMODEA, WMODEB,
BLKA, BLKB, WENA, WENB, CLKA, CLKB, RESET : in std_logic :=
'U'; DOUTA8, DOUTA7, DOUTA6, DOUTA5, DOUTA4, DOUTA3,
DOUTA2, DOUTA1, DOUTA0, DOUTB8, DOUTB7, DOUTB6, DOUTB5,
DOUTB4, DOUTB3, DOUTB2, DOUTB1, DOUTB0 : out std_logic
);
end component;

signal VCC_1_net : std_logic;
signal GND_1_net : std_logic;
signal ram_din : std_logic_vector(2 downto 0);
signal RENB : std_logic;
begin

RENB <= not (REN);

VCC_2_net : VCC
port map
(
Y => VCC_1_net
);

GND_2_net : GND
port map
(
Y => GND_1_net
);

u_counter : counter
port map
(
clk => clk_in,
reset => reset,
sel => VCC_1_net,
qa => ram_din,
qb => open
);

newCore_R0C0 : RAM4K9
port map
(
ADDRA11 => WADDR(11),
ADDRA10 => WADDR(10),
ADDRA9 => WADDR(9),
ADDRA8 => WADDR(8),
ADDRA7 => WADDR(7),
ADDRA6 => WADDR(6),
ADDRA5 => WADDR(5),
ADDRA4 => WADDR(4),
ADDRA3 => WADDR(3),
ADDRA2 => WADDR(2),
ADDRA1 => WADDR(1),
ADDRA0 => WADDR(0),
ADDRB11 => RADDR(11),
ADDRB10 => RADDR(10),
ADDRB9 => RADDR(9),
ADDRB8 => RADDR(8),
ADDRB7 => RADDR(7),
ADDRB6 => RADDR(6),
ADDRB5 => RADDR(5),
ADDRB4 => RADDR(4),
ADDRB3 => RADDR(3),
ADDRB2 => RADDR(2),
ADDRB1 => RADDR(1),
ADDRB0 => RADDR(0),
DINA8 => GND_1_net,
DINA7 => GND_1_net,
DINA6 => GND_1_net,
DINA5 => GND_1_net,
DINA4 => GND_1_net,
DINA3 => GND_1_net,
DINA2 => ram_din(2),
DINA1 => ram_din(1),
DINA0 => ram_din(0),
DINB8 => GND_1_net,
DINB7 => GND_1_net,
DINB6 => GND_1_net,
DINB5 => GND_1_net,
DINB4 => GND_1_net,
DINB3 => GND_1_net,
DINB2 => GND_1_net,
DINB1 => GND_1_net,
DINB0 => GND_1_net,
WIDTHA0 => GND_1_net, -- Idont know what these pins will do
WIDTHA1 => GND_1_net, -- means the purpose of these
WIDTHB0 => GND_1_net, -- WIDTHAn and WIDTHBn
WIDTHB1 => GND_1_net,
PIPEA => GND_1_net, -- Dont know this pin plese check and correct the map
PIPEB => VCC_1_net, -- Dont know this pin plese check and correct the map
WMODEA => GND_1_net, -- Dont know this pin plese check and correct the map
WMODEB => GND_1_net, -- Dont know this pin plese check and correct the map
BLKA => VCC_1_net, -- Dont know this pin plese check and correct the map
BLKB => RENB, -- Dont know this pin plese check and correct the map
WENA => WEN, -- Dont know this pin plese check and correct the map
WENB => GND_1_net, -- Dont know this pin plese check and correct the map
CLKA => clk_in, -- Both write and read
CLKB => clk_in, -- using the same clock
RESET => reset,
DOUTA8 => OPEN,
DOUTA7 => OPEN,
DOUTA6 => OPEN,
DOUTA5 => OPEN,
DOUTA4 => OPEN,
DOUTA3 => OPEN,
DOUTA2 => OPEN,
DOUTA1 => OPEN,
DOUTA0 => OPEN,
DOUTB8 => OPEN,
DOUTB7 => OPEN,
DOUTB6 => OPEN,
DOUTB5 => OPEN,
DOUTB4 => OPEN,
DOUTB3 => OPEN,
DOUTB2 => ram_dout(2),
DOUTB1 => ram_dout(1),
DOUTB0 => ram_dout(0)
);
end rtl;

ram_dout : out std_logic_vector(2 downto 0);
to:
ram_dout : out std_logic_vector(2 downto 0)

There are probably other things wrong from what the comments claim.

change ur entity ; part at end of the entity

entity top is
port
(
clk_in : in std_logic;
reset : in std_logic;
WEN : in std_logic; -- taken as active high
REN : in std_logic; -- taken as active high
WADDR : in std_logic_vector(11 downto 0);
RADDR : in std_logic_vector(11 downto 0);
ram_dout : out std_logic_vector(2 downto 0)
);
end top;