Synplicity / Synopsys contraint equiv

[JayJay]

synthesis define_input_delay

Are there any scripts out there to convert between synopsys constraint scripts and synplicity constraint scripts?

Also, it seems there is not a direct way to specify combinational delays (ie set_max_delay) in synplicity. Is this true? Must I use a referece to a virtual clock?

thanks all,
JJ

 

[buzkiller]

define_clock

Actually, when you set global frequency in GUI, it applies to all clocks (except gated ones) and all combinatorial paths.

regards,
Buzkiller.

 

[JayJay]

define_input_delay

So say I have a bunch of combinitorial paths:
Path A has a 7ns m@x delay
Path B has a 5ns m@x delay
Path C has a 3ns m@x delay

specifying this in synopsys is easy using the set_max_delay option.

Without over constraining paths A and B. What is the simplest way to constrain these paths in synplicity pro?

regards,
JJ

 

[buzkiller]

define_clock virtual

Are these paths fully combinatorial (from input pad to output pad) or are they between 2 registers?

regards,
Buzkiller.

<font size=-1>[ This Message was edited by: buzkiller on 2002-04-03 01:07 ]</font>

 

[JayJay]

generated clock + synplicity

They are fully combinational.

regards,
JJ

 

[buzkiller]

Here is a quote from help file of Synplify 7 :

Defining Clocks
...
5.Define internal clock frequencies (clocks generated internally) with the define_clock constraint. Apply the constraint according to the source of the internal clock.

Source : Comb. logic
Apply define_clock to... : Net. Make sure to use the n: prefix in the SCOPE interface.

regards,
Buzkiller.

<font size=-1>[ This Message was edited by: buzkiller on 2002-04-03 02:21 ]</font>

 

[JayJay]

Tried defining vertual clocks and assigning 0 input and output delays wrt the appropriate sigs. It seems the tool only looks at one clock and optimises for it. In this case vclockSlow. See constraints below:

Constraints:
#
# Clocks
#
define_clock -name {clk40} -period 25.000 -rise 0 -fall 12.500 -clockgroup clk40
define_clock -virtual -name {vclockFast} -period 10.000 -rise 0 -fall 5 -clockgroup vclocks
define_clock -virtual -name {vclockSlow} -period 20.000 -rise 0 -fall 10 -clockgroup vclocks

#
# Inputs/Outputs
#

#default i/o constraints
define_input_delay -default 0.00 -ref vclockSlow:r
define_output_delay -default 0.00 -ref vclockSlow:r

#constrain req/ack paths
define_input_delay {i*AckIn} 0.00 -ref vclockFast:r
define_output_delay {o*AckIn} 0.00 -ref vclockFast:r
define_input_delay {i*ReqIn} 0.00 -ref vclockFast:r
define_output_delay {o*ReqIn} 0.00 -ref vclockFast:r


Am I missing something here?

regards,
JJ

 

[buzkiller]

I think that you can define only one virtual clock for design, but not sure about it. Change the order of virtual clocks in your .sdc file, and if this time "vclockFast" will be the chosen one, then I'm right.
Anyway, why do you want to set the exact constraints for these combinatorial paths ? It's allrignt to overconstraint your synthesis, as long you have the correct constraints for PAR.

regards,
Buzkiller.