rats_21
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I am getting below warnings while doing "check_design" in nanotime. Can someone help me in resolving these? Its passing match_topology and check_topology stages successfully.
Warning: Because transistor xXXXM_I3_NETTRAN_3.main is a parallel transistor, delay arcs and timing checks based on delay arcs through that transistor will be removed. (TOPO-059)
check_design is completing successfully but because of above warnings, i am not able to see any timing paths in the design.
Any help will be appreciated.
TIA,
rats_21
Warning: Because transistor xXXXM_I3_NETTRAN_3.main is a parallel transistor, delay arcs and timing checks based on delay arcs through that transistor will be removed. (TOPO-059)
check_design is completing successfully but because of above warnings, i am not able to see any timing paths in the design.
Any help will be appreciated.
TIA,
rats_21