[SOLVED] Synopsys LVS Error: What does this error mean?

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Kriz Adrivan

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Hi all,

I'm doing a layout on a two-stage amplifier. However, when I run LVS, there is an error and LVS Debbuger window won't show up as it normally would. I cannot seem to fix it. Does anybody know what this error means?

**broken link removed**
 

Hi Kriz,
I couldn't get your attachment. . can you attach it properly again ??? or else can you type wats the error message that you are getting ?
 

Hi Sathishkrishna,

Thanks for the reply. Anyway, I solved it already.
In case you're wondering, the error was the portlist was not defined for the poly resistor that I was using.

I solved it by modifying my NetTran Options under the Netlisting Option tab to point to my "empty.subckt" file.

 

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