[Synopsys] ICC -> Interview Questions

Hi All,

What are interview question asked for ICC?

I'm familiar with Synopsys DC, not ICC. Would Timing and Optimization constraints be different for ICC (comparing them to DC)?

Thank you!

Hi,
Some topics you can delve in :-
1> CTS (the most important part of PnR)
2> Routing, addition of vias, fat vias, double spacing etc... NDR rules
3> placement issues and issues due to congestion
4> Low power, voltage islands, clock gating (difference between ICG and clock gating introduced by the tool)
5> Floorplanning (This needs more of practical experience) but still you can study a little bt about adding blockages.. why where, ports, pads, IO limites, core limited
6> How STA is integrated with PnR. Timing and congestion (area) are the two tradeoffs in PnR. You have to equally balance them.

Timing and optimization constraints are generally same for both DC and ICC but that would again depend on the engineer. For ex: if you feel that DC (which has better optimizing capabilities as it can see the down to the behavorial model) is over optimizing a block which is making some logic untraceble in LEC then you can place a harder constraint in ICC and leave it unconstrained in ICC.
On the other hand if you feel that some hierarchies need to be optimized to the fullest and once floorplan is done they should not be alowed to be optimized across hierarchial boundaries then you have to add additional constraints in DC and avoid it in ICC.

How does P&R different from Layout? Do they mean the same things?

From my understanding, it's hard to constrain DC to a specific area implementation, but in ICC it's possible. Correct? From another hand, it's always possible to synthesize the logic to max_area '0' and then pass the netlist to P&R guys. What tool will they use then?

As for ICC, does it has a different logic synthesis engine than DC? Is the logic synthesis and routing done on the single run in ICC or it also require two phases - logic synthesis in first place and only then routing?

What's done in the first place - gates interconnects routing or CTS?

Yes PnR and Layout mean the same thing -so to say. Actually, PnR is a subset of Layout. Layout refers to the entire process from PD to Tape out. However, for reference we all consider them the same thing.

Nothing can do a better optimization than a Synthesis tool. The reason being that you are elaborating design to convert logic into gates. The tool uses optimization techniques like K-map etc.. to arrive at very crisp gate numbers depending on your constraints. Of course max_area 0 is there but sometimes over constraining leads to challenges in LEC. So we prefer some optimization in PnR stage. Another advantage in PnR is that you have a floorplan so you can place cells that interact with each other close together and reduce the number of buffers and inverters but if the same floorplan information and DEF you provide to DC tool in topo mode it will do a better optimization.

ICC is not a synthesis tool. It has placement optimization engine, CTS opt engine and route_opt engine but these don't synthesize anything. You provide it a synthesized netlist (gate level) and it will optimize it further depending on how tight your constraints are. Placement will do so to reduce congestion while meeting timing and there is a tradeoff between congestion and area.
CTS will try to optimize timing by balancing clock paths to all flops.
Routing will try to meet all Design rule checks while utilizing all resources and diminishing all possibilities congestion on metal tracks.

PnR usually follows the following patterns :-
1> Synthesis (though not necessarily a part of Layout)
2> Pre-lay STA
3> Floorplan, Powerplan, IO plan. Die-size estimation
4> Power routing (lay all VDD, VSS, standard cell rails, Power switches etc..)
5> Placement ( std cells inside modules)
6> CTS
7> Routing
8> Metal fill
9> Signoff DRC

Thank you for your great comments! What is "Metal Fill" and why it's needed? Why Routing is done after CTS?

There are certain DFM requirements (design for manufacturability) like max density etc.. which ascertain a good yield of chips after fabrication. Metal fill is inserting redundant metal pieces between routes, vias and all wherever possible without causing any violations so as to make up for that density.
.
For any design clock is the most vulnerable element because they toggle the most and they affect a lot of flops directly (goes to CK pin) Hence, if you cannot control your clock then chances of chip failure is a lot. When you do CTS and then clock routing you are allowing the tool all the space so as to route the clocks first. Once the clocks are routed with all the rules etc.. and you are content with the routing (length, straight or crooked etc...) then you allow the tool to do the routing with the leftover resources for signal. If you do signal routing before then it will make best possible routes because all tracks would be free but then when you will route clock it will have to utilize the leftover and that could cause long deviations or crooked routes for clock and that would be a potential problem to close your timing.

Ro9ty

You provide it a synthesized netlist (gate level) and it will optimize it further depending on how tight your constraints are

Click to expand...

What constraints might be provided to ICC? For example, DC accepts Timing Constraints. What constraints are acceptable by ICC?

How do you constrain CTS? Should you define latencies, skews, min/max delays, etc?

Even ICC accepts timing constraints but i am referring to constraints on optimization engine like placeOpt -congestion or focal_opt -timing/cong etc...

Re: [Synopsys] ICC -> Interview Questions

How do you constrain CTS? Should you define latencies, skews, min/max delays, etc?

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Why Pre-P&R STA is important? Doesn't DC do STA checks while Logic Implementation/Optimization?

CTS is quite an extensive topic but just to give you a jist -> We intend to reduce the skew.. but initially it is best to start without any constraints for skew. Let the tool balance all clock paths equally. Now check for the paths with maximum latency once the clock is propagated. See what is causing that kind of latency. It could be some design issues or clock gating trying to minimize power impact etc... If you can manually fix the clock buffering on those paths then when you do a clock gating with skew objectives it will be acceptable.
Some constraints are max skew, min latency, through pins, leaf pins.
.
Pre-PnR is imp to forecast whether the timing can be closed after routing. For example if you cannot meet setup with ideal clock you can definitely not meet it after clock is propagated.
DC shows timing but timing engines of STA tools give a more precise calculation. You can check timing in ICC also but according to industry standards we follow STA in timing tools.

Ro9ty