Synopsys IC Compiler: Open Nets Error

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Brina9797

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Hi, do anyone know how to solve the open nets ( Logical Net VSS is open) error?

I obtained the error message attached below in LVS during final design checking.

 

Hi, do anyone know how to solve the open nets ( Logical Net VSS is open) error?

I obtained the error message attached below in LVS during final design checking.
The report says "Total Floating ports are 1." Is this port VSS itself?
It also says "ERROR : OUTPUT PortInst h3/c2/presentstate_reg[0] QN doesn't connect to any net." This is potentially a bigger problem.
 

The report says "Total Floating ports are 1." Is this port VSS itself?
It also says "ERROR : OUTPUT PortInst h3/c2/presentstate_reg[0] QN doesn't connect to any net." This is potentially a bigger problem.
Hi, thanks for the reply.

I had managed solved the open nets error.

However the message: " Total Floating ports are 1 and ERROR : OUTPUT PortInst h3/c2/presentstate_reg[0] QN doesn't connect to any net. " is still shown in the LVS report.

The floating ports is pointing to the error (" OUTPUT PortInst h3/c2/presentstate_reg[0] QN doesn't connect to any net. ")

May I know how to solve this problem?
 

you have to understand why this pin is unconnected. It might be possible this is from a flop with Q and QN outputs, so it is fine if one of them is disconnected.
 

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