Synopsys dve all waves are gray even simulation is running without giving any error

[dhananjayadmd]

I compiled my verilog codes with test bench files using vcs command. Then ./simv command is used to run simulation and it is also running without no errors and giving expected display messages in command window. vpd dump file is also created(amount of bytes of the vpd file is very low - 22KB). But when i view the wave form using dve command all the waves are gray with NA sign in the value column. This happens only for some codes and I cant find the reason(There is no problem with viewing wave forms for many other projects i have done in the same environment-machine) . Anyone who knows the reason or way to find the reason for this?

 

[BradtheRad]

This recent thread is about a similar question. It might have a lead or two.

https://www.edaboard.com/threads/358675/

Try a forum search on your key words of interest.

 

[dhananjayadmd]

@BradtheRad: Qs are not similar. The thread u mentioned is about xilinx ISE simulation error. My question is about Synopsys vcs. And in my case the simulation is working fine but dve wave dump is not created properly.