[Synopsys] Design Compiler (DC) vs Physical Compiler (PC) vs IC Compiler (IC)

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ivlsi

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Hello All,

Wanna anyone compare Design Compiler (DC) vs Physical Compiler (PC) vs IC Compiler (IC)? Where is a future? What are Pros & Consumption of each of the tool? Does ICC win all?

Thank you!
 

Design Compiler (DC) and Physical Compiler (PC) are synthesis tools while IC Compiler is place and route tool.
Design compiler uses wire load model (WLM) to account wire delays. Wire load models contain all the information required by compiler to estimate interconnect wiring delays. A typical Wire load model definition contains: area, resistance, capacitance, slope and fanout. Wire load model are not very accurate. Physical compiler models wire delay by doing placement of standard cell. So the delay calculation is more accurate.
IC compiler is place and route tool.

https://www.edaboard.com/threads/102787/
https://digital-ic-design.blogspot.in/2007/11/wire-load-model.html
 

DC is a synthesis tool (that convert RTL code into gate-level netlist and optimize it). It may works with WLM and with TLUplus files. The using WLM mode is an old approach to synthesis. In this mode, DC does not know abour floorplan, about real wires, so the output optimized netlist may not be suitable for PnR tool. But, when DC uses TLUplus files (for RC estimation) (you need DC topographical license for it), it works with floorplan, it do some kind of real placement (and even some kind of routing - DC graphical license), so the output netlist is optimal as input for PnR tool (for ICC).

PC is an old tool and as far as I know, Synopsys does not support it anymore.

ICC is a PnR tool, and it works well in conjunction with DC.
 
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    ivlsi

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Is DC a part of ICC? I'm familiar with DC, what skills should I purchase in order to use ICC?
 

Design Compiler (DC) & IC Complier (ICC) are two different tools from Synopsys. DC is mainly used for synthesis. ICC is used for place & route.

**broken link removed**
 

Having worked on both DC and ICC i would say both of them are equally important but ICC or more specifically PnR is more challenging.
With DC you also need to have some idea about RTL (VHDL, Verilog) etc... because it means changing a logic in harware language into gates. What we strive to achieve ultimately is a physical thing and DC is the gateway between the logical and physical side of an SoC.
Now, what you do after that is upto the PnR guys. They decide the die-size, the floorplan, the power-plan, the timing signoffs, the physical verification etc.. They also find out the errors and bugs in design of the logic. Certain things that cannot be implemented physically.
 

What are the input and output files for DC Topological and DC Graphical?

Are where special constraints are used for DC Topological and DC Graphical? How is a Floorplanning geometry passing to these tools?

Are there are special settings (libs, etc), which should be set for using these tools?
 

i/P files -> RTL files/ netlist, floorplan details (any physical info), you can take TLU+ you can use SPEF, of course libraries, - thats basically what you need.
SDC/Tcons for optimization

O/P - A lot of things - netlist, sdc, dofile for lec, svf files, etc..
 
floorplan details (any physical info)
Click to expand...
What files are used for providing Floorplan info? DEF? Milkyway? Others?

you can take TLU+ you can use SPEF
Click to expand...
Do TLU+ files consist only parasitic delays? Will the regular RC pairs to estimate the gates interconnection delays be also taken from there?
How do you say "TLU+"? Do you say it as "Ti-eL-U-plus"?

Tcons for optimization
Click to expand...
What's this? What file will it be taken from?

O/P - A lot of things - netlist, sdc, dofile for lec, svf files, etc..
Click to expand...
What's svf files? Where are they used?

What file is used in order to pass the cells placement info from DC-T to P&R tool?

Thank you!
 


DEF/MW depends on your PnR tool. If Synopsys then preferably MW, if cadence then DEF.

Yes, it contains parasitic delays. As long as your routing is not done the tool will estimate interconnect delays and that is more accurate with TLU+ than with WLMs

Tcons is constraint files like SDC (Synopsys design constraints)

SVF files are geneareted by synthesis tool which tells formality (equivalence check tool) which/ how gates are optimized so that the tool understands and hence false equivalence violations are not reported.
 
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    ivlsi

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Tcons is constraint files like SDC (Synopsys design constraints)
Click to expand...
Does Tcons format belongs to some company? Cannot find its description on the web... Could you please give some references or links about this format?

- - - Updated - - -

-> What format is used to pass the Floorplan info to DC-T?

- - - Updated - - -

TLU+ ... contains parasitic delays
Click to expand...
What's difference between the parasitic and a regular RC-extraction? Do they mean the same things?
 
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No Tcons just means timing constraints ... ususally in tcl format ... mostly used by cadence tools like RTL compiler and EDI.

DEF or Milkyway is used to pass Floorplan/Placement info

Yes sir, they mean the same. Parasitics referes to resisitance and capacitance (RC)

Cheers
ro9ty
 

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