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douglasrieger
Guest
I'm getting this message when i try to compile a sample VHDL design:
"Loading vhdl file '/home/douglas/Desktop/CarryRippleAdder.vhd'
Running PRESTO HDLC
-------------------
3: library IEEE;
^^^^^^^
[Failure] Error: Temporary vif file version mismatch. Please recompile: STD.STANDARD
*** Presto compilation was unsuccessful. ***
Error: Can't read 'vhdl' file '/home/douglas/Desktop/CarryRippleAdder.vhd'. (UID-59)
No designs were read"
Does anyone could help me with this tool?
"Loading vhdl file '/home/douglas/Desktop/CarryRippleAdder.vhd'
Running PRESTO HDLC
-------------------
3: library IEEE;
^^^^^^^
[Failure] Error: Temporary vif file version mismatch. Please recompile: STD.STANDARD
*** Presto compilation was unsuccessful. ***
Error: Can't read 'vhdl' file '/home/douglas/Desktop/CarryRippleAdder.vhd'. (UID-59)
No designs were read"
Does anyone could help me with this tool?