[SOLVED] Synopsys DC not constrainted endpoints

[soloktanjung]

Synopsys DC warnings: not constrainted endpoints for max delay

Hi,

I have these warning when do check_timing in Design Compiler:

Warning: The following end-points are not constrained for maximum delay.

End point
---------------
top/block1/async_fifo/Status_reg/data_in
top/block2/async_fifo/Status_reg/data_in
fifo1_wr_en_o
fifo1_wr_en_o

I have used set_output_delay and set_input_delay to constraint the design, but I dont understand why there are still some path unconstrained?

How to constraint it? the first two paths are not primary or top level IO ports. I use get_ports command to detect these "data_in" ports but DC cannot find it.

Thank in advance.

 

[soloktanjung]

I solved it. Use check_timing -verbose command in PrimeTime to find the paths and check the synthesize netlist. Then use set_max_delay command to constraints the paths using get_pins and get_ports in DC. I noticed that DC and Primetime report different name for the endpoints for pins.

 

[sam536]

Nont constrained end points in either DC /PT will have only Ouput ports or Data pin of the Flip flip. So you dont need to check for the ports. Ports doesnt come with hirerachy (first two pins).

how to debug these points.

Check the registers. and check the clock is reaching. If clock is not reaching, then its unconstrained.
if clock is reaching need to check below points.
a. Is there any false path to these registers.
b.Is there any disabled timing , which is masking the timing checks.
c. you might have applied max_delay dealy and may be have syntax issues.

All above that, set *unconstrained* variable to true in PT and check report_timing -exceptions all command will give better idea, why this path is unconstrained.

Regards,
Sam

 

[soloktanjung]

Hello,

Thanks for the response.

These unconstrained paths are the asynchronous path. So it is not reaching by the clock and that's why DC reported unconstrained paths. Anyway thanks for suggesting the debugging methods.

 

[er2212]

i have a questions related set_max_delay how much exactly it should be assigned means what should be the proper amount for set_max_delay because if i use it less than clock it doesn't have any effect on timing report i.e still have setup violation. other then that if i assigned more than clock some time it will take set_max_delay value into acocunt and calculate timing between two endpoints or some time it takes clock value into account and calculate timing between two point please can anybody explain me if i use set_max_delay it will not consider clock into equation.

 

[subhash_chevella]

i have a questions related set_max_delay how much exactly it should be assigned means what should be the proper amount for set_max_delay because if i use it less than clock it doesn't have any effect on timing report i.e still have setup violation. other then that if i assigned more than clock some time it will take set_max_delay value into acocunt and calculate timing between two endpoints or some time it takes clock value into account and calculate timing between two point please can anybody explain me if i use set_max_delay it will not consider clock into equation.

hi,
If, input_delay+comb_delay+output_delay > clock period, define set_max_delay

set_max_delay is one kind of exception. So, if you define max_delay on any path, clock period will not be considered for timing checks. It will use the value of set_max_delay as the available time for reaching the data from reg_out to reg_in.

In your question, you said that some times it is using set_max_delay value & some times it is using clock period value.
Can you pl tell me, how you defined set_max_delay in your script file, so that we can debug from there?

 

[er2212]

thanx subhash,

what i do is i am synthesizing asynchronous FIFO in dc compile using topdown methodology. I gave constrained and check for the violation. In dc all the timings are met and no violatioin but when i check sta in Prime Time it gives me violation in internal logic there are two points where i got violation from write pointer to fifo memory reg and from winc to fifomemory reg. so i go back DC give the same constraint then compile then gave set_max_delay -from < name of port> -to <name of port> then again compile.and after that i do not get any violation except recovery violation in primetime. what is recovery violation?

 

[subhash_chevella]

Apart from setup & hold checks in the desing, PT will verify the asynchronous timing checks as well, like recovery & removal. These checks will be performed w.r.t the pins like asynchronous clear & preset.
These pins will override any synchronous behaviour of the cell. When these pins are active, the output of the cell is governed by these pins not by the clock.

 

[er2212]

so should i clear these violations or is it ok to leave it as it is does it harm the overall design flow and if how should i clear it.

 

[subhash_chevella]

Hi,

Yes. We need to fix these violations in a similar manner as we fix setup/hold violations.
Removal violations is a kind of hold & recovery is a kind of setup.
Removal violations are critical & definitely we need to fix.

thanks,
Subhash

 

[Mahesh Shinde]

Hi ,

I am working ddr2 compiler. In ring buffer part, I am not using clock for the register flip-flops. So its not setting delays for such registers. How can set the delay delays for these registers. Her is my code.

  always @ (posedge fStrobeBar or posedge listen or posedge reset)
	 begin
		if (reset)
		  begin			 
			 F0 <= 0;
			 count <= 0;
		  end
		else if (listen)
		  F0 <= 1;
		else
		  begin
			 if(count<3)
			   count<=count+1;
			 else if (count==3)
			   begin
				  count<=0;
				  F0<=0;
			   end
		  end // else: !if(listen)
	 end // always @ (posedge fStrobeBar or posedge listen or posedge reset)
   
   assign fStrobe = dStrobe & (listen | F0);
   assign fStrobeBar = ~fStrobe;


// Capture data at the edges
// -------------------------  
   always @(posedge fStrobe)
	 case (count)
	   0: r0 <= din;   
	   1: r2 <= din;
	   2: r4 <= din;
	   3: r6 <= din;
	 endcase // case(counter)
   always @(negedge fStrobe)
	 case (count)
	   0: r1 <= din;   
	   1: r3 <= din;
	   2: r5 <= din;
	   3: r7 <= din;
	 endcase // case(counter)


// Read data
// ---------
   always @ (r0 or r1 or r2 or r3 or r4 or r5 or r6 or r7  or readPtr)
	 begin
		case (readPtr) 
		  3'b000: dout <= r0;
		  3'b001: dout <= r1;
		  3'b010: dout <= r2;
		  3'b011: dout <= r3;
		  3'b100: dout <= r4;
		  3'b101: dout <= r5;
		  3'b110: dout <= r6;
		  3'b111: dout <= r7;
		  default: dout <= r0;
		endcase // case (readPtr)
	 end // always (r0 or r1 or r2 or r3 or r4 or readPtr)
   
   
endmodule // ddr2_ring_buffer8

Please help me with this. How to set the delay for r0, r1... F0 registers.