synopsis designware: post synthesis checking

synopsys designware: post synthesis checking

Dear eda users,

does anyone know how to see which IP block synopsys maps to implement a given operator? I already know that depends on constraints if nothing different was explained. .. I would like to understand which adders/multipliers synopsys has chosen during logic synthesis.

thank you very much

David

Re: synopsys designware: post synthesis checking

Try this command report_resources.

Re: synopsys designware: post synthesis checking

oratie said:

Try this command report_resources.

Click to expand...

Thank you very much, but after synthesis the command reports

"No resource sharing information to report.

No implementations to report"

but I'm quite sure that the synthesizer uses ip core since I used operators as "+" and "*".


thank you very much,

David

Re: synopsys designware: post synthesis checking

I have never used it but have you studied the section "Reporting Resources and Datapath Blocks" in the Design Compiler® User Guide?

Currently I am looking into the Version K-2015.06, June 2015 and it seems to explain what you need! excerpt...

For large designs, analyzing one or more subdesigns can be useful. You can perform hierarchical analysis on specified designs by using the get_designs command with the analyze_datapath_extraction command:
prompt> analyze_datapath_extraction [get_designs design_list]
The analyze_datapath_extraction command generates separate reports for each specified design.
After the analysis, a report shows the contained resources in the design. This report helps to find the resources in the design source code. Note that the datapath names in this report might differ from the datapath names in the report generated using the report_resources command after compilation. However, the names of the contained resources will be the same.
For information about interpreting the resource report, see Reporting Resources and Datapath Blocks.

Re: synopsys designware: post synthesis checking

dpaul said:

I have never used it but have you studied the section "Reporting Resources and Datapath Blocks" in the Design Compiler® User Guide?

Currently I am looking into the Version K-2015.06, June 2015 and it seems to explain what you need! excerpt...

For large designs, analyzing one or more subdesigns can be useful. You can perform hierarchical analysis on specified designs by using the get_designs command with the analyze_datapath_extraction command:
prompt> analyze_datapath_extraction [get_designs design_list]
The analyze_datapath_extraction command generates separate reports for each specified design.
After the analysis, a report shows the contained resources in the design. This report helps to find the resources in the design source code. Note that the datapath names in this report might differ from the datapath names in the report generated using the report_resources command after compilation. However, the names of the contained resources will be the same.
For information about interpreting the resource report, see Reporting Resources and Datapath Blocks.

Click to expand...

thank you for these useful informations, I have read the documentation and I described the code following the "coding guide lines" they provide.

But the report commands do not show me any DesignWare instantiation... the command "analyze_datapath_extraction [get_designs pippo] gives me "Design 'pippo' does not contain unmapped DesignWare. (UISN-72)...


clicking on the error code this message is showed up:

" This error message occurs when you call analyze_datapath_extraction
command on a design that does not contain unmapped DesignWare compo-
nent. The design is either a mapped design or a design that does not
contain any inferred or instantiated DesignWare. There is nothing to be
analyzed.

WHAT NEXT
Check if the design is a mapped design."

It seems there are no DW Ip cores instantiated... but of course they should be since my high level description...

The command "report_resources" now gives me information about designware instantiated module to implement a given report... but it still does not show me which adder/multiplier it used... for instance wallace, ripple carry etc etc

Re: synopsys designware: post synthesis checking

Are you sure you are using DW components which you wish to see?

Try this...
After compiling your top level and before sythesis go to the schematic viewer. Suppose your code had the arith operation "+". A corresponding DW compenent is called "DW01_add " which is the Adder IP. Browse through the schematic viewer to see if there is the component "DW01_add " or anything with a similar name.

This is not the best approach and is not recommended for huge designs.

- - - Updated - - -

Additionally try this command...
report_synlib

In the Design Compiler® User Guide, Version K-2015.06, June 2015, see Chapter 13: High-Level Optimization and Datapath Optimization, section "Synthetic Operators", Pg 411. It is explained there how HDL operators such as + and * is handled by Synopsys DC.

Re: synopsys designware: post synthesis checking

dpaul said:

Are you sure you are using DW components which you wish to see?

Try this...
After compiling your top level and before sythesis go to the schematic viewer. Suppose your code had the arith operation "+". A corresponding DW compenent is called "DW01_add " which is the Adder IP. Browse through the schematic viewer to see if there is the component "DW01_add " or anything with a similar name.

This is not the best approach and is not recommended for huge designs.

- - - Updated - - -

Additionally try this command...
report_synlib

In the Design Compiler® User Guide, Version K-2015.06, June 2015, see Chapter 13: High-Level Optimization and Datapath Optimization, section "Synthetic Operators", Pg 411. It is explained there how HDL operators such as + and * is handled by Synopsys DC.

Click to expand...

Dear dpaul,

after the elaborate command (before synthesizing) I can see operand mapping, i.e. there is a mul_359, there is an add_255 etc.. as report_resources command has already shown. But report on what type of multipliers are used are still missing...
Actually, looking at the ref name of each component pre-synthesis, it is possible to see its "Synthetic operator", i.e. if it is a MULT_UNS_OP_32_32_33 multiplier for instance, but information about "Synthetic modules" and their "Implementations" are not present... i.e. if it is a DW02_MUL, wallace multiplier, with let's say 32 bits as inputs etc etc...
I also typed " set synlib_wait_for_design_license "DesignWare" " before analyzing, elaborating and compiling my design.

My goal is: given an algorithm, understanding the Data Flow Graph synopsys builds and which DW components it uses to build each instructions..

eg: c = a*b
e = c + d

So I'd like to see a report as: operation "*" to implement c was done using a Booth Multiplier 16x16 and to implement e was used and ripple carry adder 32+32... or for instance e was implement using a MAC since c is not an output... or something like that...

The report_resources command generates the following three reports:

• Resource report for arithmetic operators that are mapped to individual DesignWare
components
• Datapath report for arithmetic operators that are merged into a single datapath block by
datapath extraction
• Implementation report for each arithmetic cell

And it should show if a DW component it used, for me it was not the same.

This command report_synlib needs an argument, I putted there dw_foundation.sldb... it showed a list of components, there are a lot of DW ips and DW_add and DW_mul as well, so I think I'm using them... furthermore printing the variables synthetic_library and link_library, I still see dw_foundation.sldb as output.

Re: synopsys designware: post synthesis checking

So I'd like to see a report as: operation "*" to implement c was done using a Booth Multiplier 16x16 and to implement e was used and ripple carry adder 32+32... or for instance e was implement using a MAC since c is not an output... or something like that...

Click to expand...

Ok, now I understand your point.
To be honest I have never made a synth. analysis this deep, so this thread has been very interesting for me. If you still come across any unique info pertaining to this or your problem is solved then do post it here.

Let's see if there are any experts who can comment on it.

Re: synopsys designware: post synthesis checking

dpaul said:

Ok, now I understand your point.
To be honest I have never made a synth. analysis this deep, so this thread has been very interesting for me. If you still come across any unique info pertaining to this or your problem is solved then do post it here.

Let's see if there are any experts who can comment on it.

Click to expand...

thank you very much, let's keep the fingers crossed