syncronisation problem

I modified the Xilinx manchester decoder code (xapp339) in order to use command and data sync pulses in manchester enc/dec-oding.
Quick tutorial for manchester enc/dec.

Command sync pulse is 1.5 bit time high and 1.5 bit low pulse

Data sync pulse is 1.5 bit time low and 1.5 bit high pulse

Manchester one bit is 0.5 bit time High, 0.5 bit time low pulse

Manchester zero bit is 0.5 bit time low, 0.5 bit time high pulse

In my communication system, data is coming to the decoder by this order below;

1. Command Sync+9 bit manchester data,
2. Data Sync+9 bit manchester data
3. Data Sync+9 bit manchester data

This 1., 2. , 3. steps are essential for the communication, during the idle state system should send manchester zero bits.

I want to ask that how can I handle the synchronisation in order to receive the data correctly. In my code I m waiting for 6 bits then check it, if it is command sync or the data sync I m continuing to receive the bits, if it is not I reset the bit counter etc.

But I think it is not a good way because the system always sends manchester zero bits in idle state so it is hard to recognize the command sync pulse and the other data sequences if there is a shift during my 6 bits control state, I can not catch the command sync pulse.

You may see the communication profile in attachment, any help will be greatly appreciated.

regards