synchronous reset or asynchronous reset?

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owen_li

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asynchronous reset

Can somebody tell me the difference between synchronouts reset and asynchronous reset? which design style is superior? Thank you!
 

cummingssnug2002sj_resets_rev1_1.pdf

if reset is sampled to run in synchronization with clock it is called synchronous

else if reset and clock run independently it is called asynchronous design.

while working with HDLs

Asyn Reset:

//dff with async reset
`timescale 1ns/1ps
module dffasyn (clk, rst, din, q, nq);
input clk;
input rst;
input din;
output q;
output nq;
reg q;
reg nq;
always @ (posedge clk or negedge rst)
begin
if(rst==1'b0)
q<=1'b0;
else
q<=din;
nq<=~din;
end
endmodule

Snych reset:
// dff with sync rst
`timescale 1ns/1ps
module dff(clk,rst,din,q);
input clk,rst,din;
output q;
reg q;
always @ (posedge clk)
begin
if(~rst)
q<=1'b0;
else
q<=din;
end
endmodule


I think synchronous design is a better approach

go through the following link:

https://asic-world.com/tidbits/all_reset.html
 

synchronous reset

Async Reset : works immediately, as soon as it is applied
Sync Reset : waits for the clock to have effect.
Neither is superior, it depends upon application.
I would use Sync Resets everywhere in the desin to make it fully synchronus
But in some cases, when the chip is bein powered up, you dont have a clock yet, in those cases Async Reset would help.
Kr,
Avi
http://www.vlsiip.com
 

synchronous reset asynchronous reset

Download the document from internet
"CummingsSNUG2002SJ_Resets_rev1_1.pdf"
it can make you understand the diffrence clearly
 
synchronize asynchronous reset

None is superior. It all depends on your design. Both are useful at their applications...
 

synchronous asynchronous reset

asyn reset is better than syn reset.
 

asynchronous and synchronous reset

ubna said:
None is superior. It all depends on your design. Both are useful at their applications...
Click to expand...
quite right,It depends.
 

asynchronous reset and asynchronous reset

Active High asynchronous reset is prefered than the Active low Reset signal...........!!! why is it so.........
 

asynchronous / synchronous reset

I would say that 90% of the designs I see, they have Active-low Asynchronous reset.... but typically the asynchronous reset is generated with a synchronous method... but that is another story....
 

async　sync reset

Asynchonous reset or synchonous reset is based on the application.
For my application, I use asynchonous reset and reset synchonizer.

For physical engineer, they have to deal asynch. reset tree as clock tree but synch. reset as normal signal.
 

active-high synchronous

synchronus reset with simple respected clock.it is required more no of gates,and it is didnt have metastabilty problem.it is working is slow.

asynchronous reset with out respected to the clock.it is required less no .of gates.it is suffer to the metastability problem.it is working is fast

vamsi
 

asynronous reset

asynchronous reset should be insteadof synchronous reset as synchronous reset results in more gates.

Hence asynchronous reset must be used and it shoudl be synchronized.
Usually reset synchronization is done such that the assertion of reset wil be left asynchronous but deassertion of reset will be made synchronous.
 

synchronous rst

Is there anybody who can tell what is the reset synchronizer? what is the circuit structure of this synchronizer.
Thank you!
 

async reset

owen_li said:
Is there anybody who can tell what is the reset synchronizer? what is the circuit structure of this synchronizer.
Thank you!
Click to expand...

Here are some useful links regarding the reset synchronizer:


**broken link removed**
 

hi...

i have one doubt that even if we synchronize the reset, then wont there be any problem when that synchronized reset is going in design and reseting a flop in which clock is skewed w.r.t clock used in reset synchronizer....

thanks
 

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