Synchronous Reset, Is essentially???

[khaila]

fix recovery violation

Generally, Reset signal is feed-ed asynchronously, while all the ICs on a board is feed-ed by this reset.
my questions:
1. Does that reset is treated synchronously into the ASIC???
2. Is there any needs to synchronise that reset to the each internal clock domains???
3. What is the worst cases in working with Asynchronous reset internally???
4. If we assume we should synchronize the reset, whats should be its period??? is one clock enough or more???
5. If the reset is supposed to be synchronous one, should I insert it to the sensitivity list???

Khalil.

 

[asicengineer1]

reset recovery violation

3.metastability, as it is asynchronous in nature.
4.for synchronizing, a double-flopping methodology is used. but, usually, just like its discussed before, asynchronous assertion and synchronous deassertion of reset is used.
5.if its synchronous, i don't think it should be included in sensitivity list.

correct me if i'm wrong.

 

[bharat_in]

1. Does that reset is treated synchronously into the ASIC???
>>No, on ASIC also it will work asynchronously...

Plz, correct me if i'm wrong.

 

[sameer_dlh25]

1. Does that reset is treated synchronously into the ASIC???

Yes Reset is synchronized and usually it's asertion is asynchronous while deassertion is syncronous.

2. Is there any needs to synchronise that reset to the each internal clock domains???

to avoid metastbility.

4. If we assume we should synchronize the reset, whats should be its period??? is one clock enough or more???

It should be atleaset 2 clocks and if in your design reset prpogates throgh non reset flops then even more.

5. If the reset is supposed to be synchronous one, should I insert it to the sensitivity list???

if assertion is asynchronous then yes reset should be there in sensitivity list.
if assertion and deassertion both are totally synchronous then you need not to define in sensitivity list.
I hope this will help

 

[khaila]

4. If we assume we should synchronize the reset, whats should be its period??? is one clock enough or more???

It should be atleaset 2 clocks and if in your design reset prpogates throgh non reset flops then even more.

May you explain why it should be at least TWO clocks????


Khalil.

 

[sameer_dlh25]

As I mentioned assertion of reset in asynchronous and desertion is synchronous.
To achieve this functionality we use reset synchronizer circuit with two flops.
(In brief reset synchronizer uses back to back connected flops.)


To make sure reset got propagated through this circuitry it should be of atleaset of two clock cycle.

I hope this will help:|

 

[khaila]

As I mentioned assertion of reset in asynchronous and desertion is synchronous.
To achieve this functionality we use reset synchronizer circuit with two flops.
(In brief reset synchronizer uses back to back connected flops.)


To make sure reset got propagated through this circuitry it should be of atleaset of two clock cycle.

I hope this will help:|

Thanks for the effort but I am missing you!!!
what do you main by TWO clocks:
1. Is it beacsue the synchronizer that uses two FF so the reset signal has latecny???
or
2. You are widening the reset signal to be two clock width???

Khalil.

 

[sameer_dlh25]

khaila,

You take it like this assertion is Asynchronous that means there is a fair probability that flops in the design receive the improper logic level of reset.(voltage level between and 1 & 0 levels).
If you keep reset only for one clock it will take long time to recover from metastability.If we keep reset low for one more clock that means providing the proper voltage level to flops in the next clock so that it can recover from metastability.
Correct me if I am wrong

 

[khaila]

khaila,

You take it like this assertion is Asynchronous that means there is a fair probability that flops in the design receive the improper logic level of reset.(voltage level between and 1 & 0 levels).
If you keep reset only for one clock it will take long time to recover from metastability.If we keep reset low for one more clock that means providing the proper voltage level to flops in the next clock so that it can recover from metastability.
Correct me if I am wrong

If I understood very well:
1. In a chip we have to work work with RESET synchronously.
2. To synchronize that RESET signal we should use a synchronizer with TWO FF (typical synchronizer).

Now:
Why we should work with the RESET synchronously??? Every FF has its input RESET and it works asynchronously so why we need to work synchronously???
I can't understand!!!

Another issue:
Supposed we should synchronize the RESET. But what happened if the current input RESET's period is less than one clock??? which it is possible!!!
Is it mean that we should widen the RESET pulse???

Added after 6 minutes:

3.metastability, as it is asynchronous in nature.
4.for synchronizing, a double-flopping methodology is used. but, usually, just like its discussed before, asynchronous assertion and synchronous deassertion of reset is used.
5.if its synchronous, i don't think it should be included in sensitivity list.

correct me if i'm wrong.

If FF has its RESET input. By-default that input is treated asynchronously. so how metastability will occur???

 

[sameer_dlh25]

Read this first
It should be useful to you

**broken link removed**

 

[abhikohli]

@Sameer u've given all answers beautifully. However I'd like to add few points:
- Async Reset is async period. We need to fix our reset strategy if we want 2 use async or sync reset quite early on in design. In async it has higher priority than all other signals including clk. So it wont throw ur design in metastabilty. Only constrain is that reset pulse width should meet minimum timing of library element. (How can anyone achive 2 clk reset pulse width if clk is not running). Deasserting of reset has to be in sync with clk to prevent reset-recovery violation.(This is where reset-sync comes into picture, so that means in a clk domain async will be asserted immediately but will be deasserted after 2 clocks.)

Added after 4 minutes:

-If you need sync. reset you won't put it in sensitivity list.

Another thing, never treat HW designing as same as SW designing. U need to make sure whats ur design before coding, Its not that if I need this let me try adding/removing this from code. HDL are HW description Languages so u should be very clear what is the design u want to describe. I am saying this here b'cos u need to make sure how u r going to add sync to design NOT by simply adding removing it from sensitivity list.

 

[FLEXcertifydll]

generatly do't use syn-reset, based on ur design, U are sure about that there need syn-reset.
In PT recover/remove check is different.