Synchronous n-bit counter, overall propagation delay (CLC input to RCO output)

[pAdoX]

Hello i am supposed to construct a precision 3ms gate time.

My idea is to use four cascaded synchronous counters of the type sn74als161b.
The CLK input is a 16MHz precision clock.

here are my questions:

Q#1: How do I calculate the overall propagation delay for the n-bit counter?


Is it a summa of every stages CLK to RCO/TC propagation delays?

Q#2: I would like to use the last stages RCO/TC to reset a FF. During my research on sync 161 counter i've looked at MC74AC161-D data sheet and i read this:
"The TC output is subject to decoding spikes due to internal race conditions and is
therefore not recommended for use as a clock or asynchronous reset for flip−flops, counters or registers."

In the sn74als161b datasheet there is nothing written about spikes - does this mean that unwanted spikes can't happen on the last stage of a cascaded counter (sn74als161b)?

THANK YOU FOR YOUR HELP
View attachment MC74AC161-D.PDFView attachment sn74als161b.pdfView attachment MC74AC161-D.PDFView attachment sn74als161b.pdf

 

[FvM]

In the sn74als161b datasheet there is nothing written about spikes - does this mean that unwanted spikes can't happen on the last stage of a cascaded counter (sn74als161b)?

RCO isn't intended for asynchronous use. Spikes have to be always expected for combinational signals. RCO can be used as a synchronous signal or needs to be registered.

It should be supplemented that TTL designers often didn't care for rules of synchronous logic. Instead they put small capacitors at arbitrary places to suppress spikes.