synchronous frequency divider design.

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nathanee

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Hi all,

Please help to suggest reference circuit or paper of SYNCHRONOUS frequency divider design, which is 8-bit.

The design should be schmatic entry instead of HDL.

Thanks in advance.

BRs,
-nathan
 

what fequency u want to achieve?
 

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    nathanee

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The frequency is used in PLL, thus the frequency range is from 100MHz to 500MHz.

BR,
-nathan
 

I mean to ask... say your input frequency is X. then what is the output frequency interms of X required for the freuency divider .
 

which reference book i can refer?
 

hi,

This a paper named "Clock Dividers Made Easy".
SNUG Boston,2002.
 
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