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For level resets, async has the reset when the level is reached. in sync reset the level has to be there at least as long until the next clock comes along and the reset is done then. In both, the level has to stay there for a certain time after the reset or unusual things may happen.
I guess everything was said by sunjimmy and flatulent, but the things are always better to explain in more views, so that the practical consequences became completely clear:
Asynchronous reset (often also caller "clear") does reset /clear the state imediately, independently of the clock edges. It usually overrides any clock-synchronized actions, so it keeps the system/component firmyin "reset-state" while active.
Synchronous reset is always related to the clock active edge. It is for a register equivalent of loading with "reset-value" - usually zeros. It has no effect outside the active clock edge (just be aware setup and hold times around the edge -see below).
The sister functions: synchronous preset / asynchronous preset behave similarly, except they set a register's value (usually) to "1" instead of "0". Thus the asynchronous one is more powerul than the synchronous one and always immediate in it's action.
As flatulent points out, having pulses too narrow and not respecting setup time/hold time for the synchronous signal, may lead to something called metastability, and the consequences can be quite unexpected, and completely unpredictable. Therefore, if the synchronous reset/preset is not stable at/near the clock edge (i.e. stable before "setup time" or until "hold time"), or the pulse is shorter than the data sheet minimum, be aware! The result will not be predictable nor reliable.
Hi,
I think in ASIC design, use Asyn reset or syn reset is mostly depend on library cell. Normally, register cell in standard library is asyn reset, so you had better to use asyn reset. But be careful the race condition happed.
But syn reset is good if your library has syn reset register.
Some have only clear others have clear and preset inputs. It is all a matter of what your overall circuit needs. For instance, if you are making a timer, the circuit is set to all zeros (clear) before the timing starts. Some counters have a load input so that it can be set to a specific value. The loads can be sync or async. A common divide by N system loads a given number and counts down. When the count reaches all zeros, the borrow is fed around to load.
Several decades years ago the TTL logic was a most popular. In HIGH output power consoption was less then out is LOW - traditionally reset and other short sygnals are LOW. But now it is only designer decision and consideration - you can use a HIGH level for reset or LOW as you want
Hi ,
I think the high reset or low reset is depend on the standard cell library you use. If in library there only exist flipflop have low reset pin , so you had better use low reset ,otherwise you have to use a unnessesary NOT cell.
In the most Designs you use a asynchronus reset and a synchron design.
If you use asynchronus busses like a VME-Bus you need to synchronize them for your Design!
Asynchronus Designs are complicated to handle, because you can have delays between signals!!
Phytex
I agree with you Phytex: I also use asyn. rst and sync design. The few times I had to include asynchronous parts in my designs, all were problems until I developed synchronizers able to communicate async. logic with the synchronous one. Timing analysis was quite critical.
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