Synchronous and asynchronous clock relationships

If you look at both clock simultaneously with an oscilloscope (triggering on one) you can readily see if the two clocks stay the same with respect to each other.
If they drift in phase/frequency with each other than they are not synchronized.

If two clocks are generated from the same source, have the same frequency and the same phase, they are assumed to be synchronous.
If you deviate from any of the above three, then the clocks are not synchronous any more!

dpaul said:

If two clocks are generated from the same source, have the same frequency and the same phase, they are assumed to be synchronous.
If you deviate from any of the above three, then the clocks are not synchronous any more!

Click to expand...

Hi Paul,
Thanks for the explanation.
I have a small doubt here.
Does generated clock remains in the same phase as main clock?
As I know main clock and generated clocks are synchronous to each other.

Thanks,
Karthik

dpaul said:

If two clocks are generated from the same source, have the same frequency and the same phase, they are assumed to be synchronous.
If you deviate from any of the above three, then the clocks are not synchronous any more!

Click to expand...

Not true. Being in phase is not a requirement for being synchronous. Two clocks, 90 degrees out of phase, are used all the time. And they are synchronous.

The only phase requirement is that the phase between the two signals remains constant.

Also clocks with rational frequency relation and fixed phase can be treated as synchronous, e.g. the 2xF0 and 3xF0 outputs of a PLL. Timing analysis is regularly calculating setup and hold time for transfers between both clock domains.

In general, this is what I have seen when it comes to multiple clocks. Dont read the points in isolation as they are related to the other points

1) two clocks when generated using same PLL's will not have any drift/wander/PPM
2) for point above, they can have different phases
3) when two clocks are generated using 2 different PLL's but using a common reference then point 1 and 2 will still apply. Additionally, the 2 clocks can have different jitters due to different characteristics of the PLL's
4) when two clocks are generated using 2 different PLL's and they use different reference (even though they are nominally within a certain range) these clocks can have different phase, jitter but more importantly, they can be PPM differences. That is, from time to time, these 2 clocks can be off by a PPM value

As a additional point for point 4) above, if you are interfacing 2 independent systems then this situation will come because you cannot distribute a common reference clock to both the system. Same case applies when the systems are far apart. For example, an ether switch and a laptop connecting to it. There is no way to have a common clock distributed to these 2 systems. You have to live with PPM differences in such cases.