Synchronizing and reading off falling edge

[hithesh123]

I have an external clock, based on its falling edge I have to clock-in data (16 bits).
After clocking in 8 bits, based on the data value, the subsequent 8 bits have to be stored in different registers.

Can I clock-in all 16bits at the same time or should I do 8bits and then remaining 8.
In a process already using rising_edge, how do I clock-in the data based on falling edge of external clock.

 

[barry]

I have an external clock, based on its falling edge I have to clock-in data (16 bits).
After clocking in 8 bits, based on the data value, the subsequent 8 bits have to be stored in different registers.

Can I clock-in all 16bits at the same time or should I do 8bits and then remaining 8.
In a process already using rising_edge, how do I clock-in the data based on falling edge of external clock.

You leave a lot of questions unanswered.

I assume you are targeting an FPGA.
What is your speed?
Most importantly, is your data synchronized with the clock?
How many registers, 256?
I'm assuming the 16-bits are parallel, right?

One way of doing this is you can use the lower 8 bits as the input to a data selector whose outputs are used as latch-enables for your registers.

 

[hithesh123]

I assume you are targeting an FPGA.
yes.
What is your speed?
speed of data in is 10MHz

Most importantly, is your data synchronized with the clock?
No.

How many registers, 256?
8-12 max.

I'm assuming the 16-bits are parallel, right?
16 bit serial.

 

[barry]

If your data is serial, how were you intending to clock in all 16 bits "AT THE SAME TIME"???

1) You are going to have to synchronize your data. You'd better read up on that.

2) You can still use the approach of having the first 8 bits go to a data selector. The following 8 bits would then be shifted into the register selected by your first 8 bits.

 

[hithesh123]

If your data is serial, how were you intending to clock in all 16 bits "AT THE SAME TIME"???

No no. I am clocking in all 16 bits at the same time. It will be one data bit at a time.
Just think about an SPI Slave. Let's say the data is 16bits. The first 8bits contain register address and remaining 8 bits are the register content.

If the FPGA is the SPI slave, then I'll have to clock-in data serially based on the edge of the SPI clock.
At the same time, I have to decode the register address.
What you mentioned will work. But want to if there are other options.

 

[FvM]

I fear you didn't yet manage to ask a clear question.

I understand that the question is related to a standard problem, how to transfer data between the external SPI clock and and internal FPGA clock domain?

As in any clock domain crossing proper synchronization must be provided. There are basically two approaches:

- For slow and medium SPI clock speeds, all synchronous processing is performed in the system clock domain after synchronizing the SPI signals to the system clock. Particularly, synchronous edge detection for SCK has to be performed. Can work with system clocks > 4* SPI clock frequency.

- For fast SPI clocks, the shift register must be operated by SCK directly. Parallel data have to be transferred consistently to and from the system clock domain. Different domain crossing methods are possible, implementation details depend on the system's data model. Latencies of the data synchronizer can be a problem, e.g. if an address word selects read data. In simple cases, all write and read data are registered in the SPI clock domain and transferred while the SPI bus is inactive to guarantee consistency (locking method).

 

[hithesh123]

I understand that the question is related to a standard problem, how to transfer data between the external SPI clock and and internal FPGA clock domain?

As in any clock domain crossing proper synchronization must be provided. There are basically two approaches:

- For slow and medium SPI clock speeds, all synchronous processing is performed in the system clock domain after synchronizing the SPI signals to the system clock. Particularly, synchronous edge detection for SCK has to be performed. Can work with system clocks > 4* SPI clock frequency.

.

Yes. I plan to synchronize the SPI clock with FPGA clock.
Sychronous edge detection meaning - use something like a dual rank synchronizer?

How do you clock in the data? Use rising_edge(SPI clk) ?

 

[FvM]

Yes. I plan to synchronize the SPI clock with FPGA clock.
Sychronous edge detection meaning - use something like a dual rank synchronizer?

A "dual-rank" synchronizer and another FF to check for rising respectively falling edges by comparing present and previous state. All FFs clocked from the system clock.

How do you clock in the data? Use rising_edge(SPI clk) ?

That's the method opposite to synchronous edge-detection, "operating the shift register by SCK directly". It requires consistent transfer of parallel data to and from the system clock domain.

 

[hithesh123]

Here's the vhdl code that uses Barry's suggestion. The process runs only when sclk changes.
First 8 bits are stored in data_reg. These bits contain address of control/config regs.
After 8bits are clocked-in, its decoded and subsequent bits are directly stored in control/config regs.

process(sclk,rst)
Begin
	if(rising_edge(sclk)) then
		count=count+1;
		data_reg<=data_reg(6 downto 0) & sdata;
		
		if(count>=8) then
			//start decode
			case DATA_REG is
			  when "01" => 
				
				control_reg1<=control_reg1(6 downto 0) & sdata;

			  when "02" => 
				
				control_reg2<=control_reg2(6 downto 0) & sdata;
                          
			  when "03" => 
				
				control_reg3<=control_reg3(6 downto 0) & sdata;

			  when "04" => 
				
				control_reg4<=control_reg4(6 downto 0) & sdata;

			  when others =>
				
		


		end if;
	end if;
end process;

That's the method opposite to synchronous edge-detection, "operating the shift register by SCK directly". It requires consistent transfer of parallel data to and from the system clock domain.

I don't understand. you mean

if (rising_edge(sclk) then
  data_reg<=data_reg(6 downto 0) & data;