synchronization of asynchronous reset

Let us first discuss the last diagram in the asic-world link. The diagram shows how an asyn reset being syncronized. Now this synchronized reset can be sent to all flipflops of a design. What I mean is that, this synchronous reset will be connected to all asynchronous reset pins of each of the flipflops in the design such that the flipflops will be reset synchronously. In this mechanism there will not be any necessity of a MUX or AND gate in front of the flipflop input for reset to happen synchronously.

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I completely agree.

FVM

Since now you agree, please answer the following

What are the advantages and disadvantages of doing synchronous reset in a fully synchronous design as depicted in the last diagram in the above link over doing synchronous reset by adding a MUX or AND gate in front of the flip flops?

The Sunburst paper does not discuss the answer of the above question.

Regards

Two points:
- As previously stated, I don't agree with the classification of the circuit as "fully synchronous reset". It's an asynchronous reset with a synchronized reset signal. The essential point is to release the asynchronous reset input of all FFs synchronous to the clock to avoid unpredictable states.
- I explained the advantage/disadvantage in post #19:

The sunburst paper also discusses disadvantages of the synchronous reset, it probably doesn't emphasize the most obvious one in FPGA designs: Needing an extra input term to the combinational logic in front of each FF instead of the always implemented asynchronous line.

The latter is a sufficient reason to rely on (synchronized) asynchronous resets for all regular FFs and turns the advantages/disadvantages discussion into a mostly theoretical thing as far as everydays FPGA design is involved.

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FvM said:

Two points:
- As previously stated, I don't agree with the classification of the circuit as "fully synchronous reset". It's an asynchronous reset with a synchronized reset signal. The essential point is to release the asynchronous reset input of all FFs synchronous to the clock to avoid unpredictable states.

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But here also metastability issues doe not come into play when the async reset is removed. Do not you see that?

I see the following advantages of this synchronous reset and this is not discussed in Sunburst paper:

This implementation require lesser number of gates compare to usual implementation of sync reset with one 2:1 mux in front of each D flipflop. Do you see this?

But here also metastability issues doe not come into play when the async reset is removed.

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Possible timing violations or even metastability haven't been discussed in this thread yet. Both designs can achieve correct timing, in so far there's no advantage/disadvantage.

I see the following advantages of this synchronous reset and this is not discussed in Sunburst paper:

This implementation require lesser number of gates compare to usual implementation of sync reset with one 2:1 mux in front of each D flipflop.

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I stated the same, please review post #19.

FvM said:

The last diagram in the asic-world link doesn't show "a fully synchronous design". It shows a reset synchronizer to be connected to the asynchronous reset inputs of all regular design FFs. Besides minor differences it corresponds to the function of Figure 6 in the sunburst paper.

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This Figure 6 is a standard synchornizer and is for resetting a system asynchronously, so I do not agree to say that it corresponds to the last diagram in the asic-world link except minor difference.

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FvM said:

The latter is a sufficient reason to rely on (synchronized) asynchronous resets for all regular FFs and turns the advantages/disadvantages discussion into a mostly theoretical thing as far as everydays FPGA design is involved.

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What are you referring to by stating latter which is the second word in the first sentence in the above quote?

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FvM said:

Possible timing violations or even metastability haven't been discussed in this thread yet. Both designs can achieve correct timing, in so far there's no advantage/disadvantage.

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But, do you agree even the last diagram in the asic-world link does not suffer from any metastability issue?

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FvM said:

The sunburst paper also discusses disadvantages of the synchronous reset, it probably doesn't emphasize the most obvious one in FPGA designs: Needing an extra input term to the combinational logic in front of each FF instead of the always implemented asynchronous line.

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How is this advantageous in FPGA design. Do you agree that it is an advantage in ASIC design also as the last diagram in the asic-world link requires lesser number of gates?

The common features of both circuits:
- they are intended to feed the asynchronous reset line of the design
- both release the reset synchronous to the clock

The differences:
- Sunburst figure 6 resets the system immediately when the primary reset input is asserted, with or without a clock
- Asic world needs a clock to reset the system. It also activates the asynchronous reset line synchronous to the clock.

The relevance of the different features has been discussed in your previous thread https://www.edaboard.com/threads/226729/ 18 months ago, mostly by other contributors and I don't feel appointed to retell all arguments. I'll restrict myself to tell my viewpoint about reset synchronizers.

I'm using a reset synchronizer according to sunburst figure 6 in all FPGA designs. It's essential in most designs to get an immediately acting reset input without a clock, e.g. to set a safe state of all outputs. I'm not aware of a situation where asynchronous reset assertion involves a problem.

FvM said:

I'm using a reset synchronizer according to sunburst figure 6 in all FPGA designs. It's essential in most designs to get an immediately acting reset input without a clock, e.g. to set a safe state of all outputs. I'm not aware of a situation where asynchronous reset assertion involves a problem.

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Why is it essential to get an immediately acting reset input without a clock?


It seems, you did not answer my following query against your comment

The sunburst paper also discusses disadvantages of the synchronous reset, it probably doesn't emphasize the most obvious one in FPGA designs: Needing an extra input term to the combinational logic in front of each FF instead of the always implemented asynchronous line.

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How is this advantageous in FPGA design. Do you agree that it is an advantage in ASIC design also as the last diagram in the asic-world link requires lesser number of gates?

It seems you have not also replied my following query. The quote below is the last paragraph of your post no. 19.

The latter is a sufficient reason to rely on (synchronized) asynchronous resets for all regular FFs and turns the advantages/disadvantages discussion into a mostly theoretical thing as far as everydays FPGA design is involved.

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What are you referring to by stating latter which is the second word in the first sentence in the above quote?