synchronization of asynchronous reset

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sun_ray

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In the foollowing link, at the end a good suggestion have been provided to provide synchronous rest to the flipflops of a design. At the end also they have depicted the picture where a async reset is synchronized to sync reset. What about the reset of both flipflops in the last diagram where it is depicted how an async rest is synchronized to sync reset?
 

The purpose of reset synchronization is "Reset can be applied asynchronous, but reset removal should be synchronous to the clock". Reset synchronizer will ensure that "When reset is asserted, all the flops will reset asynchronously, when reset is de-asserted , it takes 2-clock cycles to remove reset.
 

Actually tha last figure shows a 2 Flop synchroniser that is used to bring the asynchrous signal which is the async. reset to the synchronous domains (that of the clock).
 

FVM, Rocking_vlsi, AdvaRes

Do you want to mean that the said reset mechanism that is depicted at the last of the attached documen will not work?
 

sun_ray said:
FVM, Rocking_vlsi, AdvaRes

Do you want to mean that the said reset mechanism that is depicted at the last of the attached documen will not work?
Click to expand...

It will works but it's the matter of your digital block. If you have design based on synchr. rest you have to synchronize your reset input (coming from outside). But if your design is based on asynchr. reset you have to (or you should) synchronize your reset removal.
 

Do you want to mean that the said reset mechanism that is depicted at the last of the attached documen will not work?
Click to expand...
The synchronizer will work - with the restrictions discussed in your previous thread.
 

FVM

Which previous thread are you talking of? Please provide the subject line.

Regards,

- - - Updated - - -


Can Rocking_vlsi, AdvaRes comment on this? I thank Jirika for his comment.

BUT, THE QUESTION STILL REMAINS THAT "At the end also they have depicted the picture where a async reset is synchronized to sync reset. What about the reset of both flipflops in the last diagram where it is depicted how an async rest is synchronized to sync reset?"

- - - Updated - - -

ANOTHER QUESTION:

What are the advantages and disadvantages of doing synchronous reset in a fully synchronous design as depicted in the last diagram in the above link over doing synchronous reset by adding a MUX or AND gate in front of the flip flops?
 


Well let them unconnected. You cannot connect them to the left side asynch. reset and also you cannot connect them to the right side synch. reset, right?
 

jirika said:
Well let them unconnected. You cannot connect them to the left side asynch. reset and also you cannot connect them to the right side synch. reset, right?
Click to expand...

Yes. So I ask how I can reset those flipflops. There can be need sometime for the reset of these two flipflops. How can I reset them?

- - - Updated - - -

FvM said:
See post #4.
Click to expand...

I think you are mentioning the following thread

http://www.asic-world.com/tidbits/all_reset.html

But in the above link there is no discussion of about any restriction on the reset mechanism that is depicted in the last figure.

Regards
 

I think you are mentioning the following thread
Click to expand...
No I'm referring to your previous thread https://www.edaboard.com/threads/226729/, also linked in post #4.

In this thread, the standard reset synchronizer design is discussed which resets the synchronizer FFs asynchronously, in contrast to the circuit suggested in asic-world.
 


But this synchronizer will be useful if the design has asynchronous resest. How will you provide a reset when you have a completly sincgronous design? This is the main idea os starting the thread. So, I also asked "What are the advantages and disadvantages of doing synchronous reset in a fully synchronous design as depicted in the last diagram in the above link over doing synchronous reset by adding a MUX or AND gate in front of the flip flops? "

Regards
 

But this synchronizer will be useful if the design has asynchronous reset.
Click to expand...
I didn't opt against a synchronizer.

It seems to me that the discussion goes in circles, everything has been said 18 months ago. You stated to know the sunburst paper linked in your previous thread http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_Resets.pdf

The paper addresses all relevant questions brought up anew like adavantages and disadvantages of different reset schemes. It also suggest a standard reset synchronizer in Figure 6.
 


But the paper does not discuss what I asked, "What are the advantages and disadvantages of doing synchronous reset in a fully synchronous design as depicted in the last diagram in the above link over doing synchronous reset by adding a MUX or AND gate in front of the flip flops? "

Regards
 

It depends on application.
The mux solution require less transistor to be implemented. More, it consume less dynamic power because in the last solution where a flip flip is used.
 

I think the paper does discuss this configurations. There might be misunderstandings involved.

The last diagram in the asic-world link doesn't show "a fully synchronous design". It shows a reset synchronizer to be connected to the asynchronous reset inputs of all regular design FFs. Besides minor differences it corresponds to the function of Figure 6 in the sunburst paper.

The "MUX or AND gate in front of the flip flops" in the second last asic-world digram represents a fully synchronous reset, corresponding to Figure 1 to 3 in the sunburst paper. (The paper is discussing other detail problems related to this figures, beyond the scope of this thread).

The sunburst paper also discusses disadvantages of the synchronous reset, it probably doesn't emphasize the most obvious one in FPGA designs: Needing an extra input term to the combinational logic in front of each FF instead of the always implemented asynchronous line.

The latter is a sufficient reason to rely on (synchronized) asynchronous resets for all regular FFs and turns the advantages/disadvantages discussion into a mostly theoretical thing as far as everydays FPGA design is involved.
 


FVM

Let us first discuss the last diagram in the asic-world link. The diagram shows how an asyn reset being syncronized. Now this synchronized reset can be sent to all flipflops of a design. What I mean is that, this synchronous reset will be connected to all asynchronous reset pins of each of the flipflops in the design such that the flipflops will be reset synchronously. In this mechanism there will not be any necessity of a MUX or AND gate in front of the flipflop input for reset to happen synchronously.

Please correct me if my understanding is wrong.

Regards
 

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