Sync / Async clock domains -> how to define?

[ivlsi]

Hi All,

I have two clock domains - clk1 and clk2.

The clk2 was generated from clk1 and its frequency is 3/5 of clk1.

Could these clock domains be considered as synchronous? If they are could not be, then why?

Thank you!

 

[FvM]

You can define it synchronous (e.g. as clock group) if the skew is low enough and the logic is able to run at 3 times clk1 frequency. Timing analysis will care for.

 

[morris_mano]

If you have 2 different generated clock from same source with different frequency, the phase difference is constant between these clocks and they are considered source synchronous. During timing analysis, if you specify them as generated clocks then tool will try to balance the skew and does have information about phase to do proper setup and hold checks.

 

[ivlsi]

So, what's the definition for the asynchronous clock (besides the case they are generated not from the same source)?

When must I consider the clocks as asynchronous even they were generated from the same source?

Thank you

 

[morris_mano]

I missed the part "clk2 being 3/5 of clk1". If the phase between clk1 and clk2 varies because of their frequency even with the same clock source, then they needs to be treated as asynchronous. For example, 50MHz and 37MHz clocks (whose phase relationship changes over time) needs to be defined as two separate clock domains even if share the same source.

 

[ads-ee]

I missed the part "clk2 being 3/5 of clk1". If the phase between clk1 and clk2 varies because of their frequency even with the same clock source, then they needs to be treated as asynchronous. For example, 50MHz and 37MHz clocks (whose phase relationship changes over time) needs to be defined as two separate clock domains even if share the same source.

Well in the case of the clk2 being 3/5 of clk1, FvM is correct in saying that the timing must met 3x the frequency of clk1, as that is the minimum relationship between the two rising edges. So yes you could treat them as synchronous, but might have trouble meeting timing depending on the clk1 frequency you're starting with.

 

[FvM]

Two clocks with integer frequency ratio n:m are not per se asynchronous. The phase is varying stepwise with a minimal launch to latch delay according to the least common multiple of both clock. It can be well manageable for 3:5, but hardly for 37:50.

 

[ads-ee]

In FvM's example of 37:50 you would probably have no problems if the clocks in question were 3.7 MHz and 5 MHz as they would have a phase relationship between them that would require at least a 185 MHz timing between the two clocks. If the clocks are 370 MHz and 500 MHz....well I don't think even Intel's planned roadmap to 5nm will give us 18.5 GHz logic.

 

[ivlsi]

Re: Sync / Async clock domains -> how to define?

if the clocks in question were 3.7 MHz and 5 MHz as they would have a phase relationship between them that would require at least a 185 MHz timing between the two clocks

Could you please explain how you got 185MHz? What's the calculation? How can I calculate the minimum relationship between the clock phases?

- - - Updated - - -

Well in the case of the clk2 being 3/5 of clk1, FvM is correct in saying that the timing must met 3x the frequency of clk1

Why x3? could you please explain? Thank you

 

[ads-ee]

FvM said it in post #7. least common multiple.
3:5 lcm is 15: hence the 3x requirement on the faster clock.
37:50 lcm is 1850, scaling 3.7, 5, and 185

 

[FvM]

It's the least common multiple in both cases, the smallest frequency that can generate both clocks when divided by integer factors.