symmetric buffers and inverters

[deh_fuhrer]

Why do we use symmetric buffers and inverters in clock tree synthesis???

 

[onlymusic16]

The answers is in your question. What is the need of clock tree synthesis? Hope you got it now!

 

[deh_fuhrer]

but still i didnt get dat....can u explain it briefly....

 

[phutanesv]

Dear deh_furher,

Buffers are used to insert delays


while inverters are used to geneate the invertion of clock need in circuits


Regards
phutane

 

[deh_fuhrer]

Dear deh_furher,

Buffers are used to insert delays


while inverters are used to geneate the invertion of clock need in circuits


Regards
phutane

ohh...I think you didn't get my question....Sorry for so brief question, let me ask it again, why do we use symmetric inverters and buffers instead of normal inverters and buffers in clock tree synthesis????

 

[hfooo1]

hi

cause we require steady duty circle

 

[onlymusic16]

Here you go...

Clock nets being of higher frequency are more sensitive with regard to timing - transition rise, fall times etc. Hence clock buffers have equal rise and fall slew rates, On the other hand, normal buffers are designed with p/n ratio such that sum of rise delay and fall delay is minimum (atleast for high speed libraries)

Reason for doing this(symmetricity) is to prevent duty cycle of clock signal from changing when it passes through a chain of clock buffers.

Hope this helps!

 

[shavakmm]

as you all know that goal of CTS is to meet skew target or in otherwords to achieve minimum skew.
To accomplish this we insert buffers in clock path. Now if buffers have different rise and fall time it will affect clock duty cycle... with this condition also tool can do skew optimization.... but it complicates the whole optimization process as tool has to deal with clock with different duty cycle at different flop paths.

If buffer delays are same only thing tool has to do is to balance the delay by inserting buffers.... skew balancing algorithm may be local skew or global skew optimization as you select it.

rgds
https://asic-soc.blogspot.com

 

[ericyuan]

clock buffer and invter are designed in library.....they have equal rise/fall time
so you just want to control the clock latency and transition,right?

 

[phutanesv]

Dear Deh_furher,

In case of normal buffer the rise and fall time may not remain same

Similarly we hav clock buffer the rise and fall time remai the same

we make use of this in CTS fro clock routing.
Symmetric buffer in a sense that if we want symmetrical rise and fall time we
have to do that.

hope i clearde u

phutanesv

 

[iwpia50s]

If a clock tree is synthesized with all buffers, and an inverted clock is not needed, then an imbalanced buffer does not impact clock duty cycle. The main reason symmetric buffers are used in a clock tree is power. The clock is the most active signal in a design and since slow transitions increases power, clock buffers are symmetric with minimized slews to minimize power.

 

[csmode]

hey clk buffers dessipate more power than normal buffers.