Symbol Timing Recovery in FPGA

Hello all,

Through my frustrations and heading back here over and over again for references and suggestions today I'm posting my first thread here in need of desperate help.

I had a similar problem with costas loop before. I then scratched my head against the walls (i know i am not that bright) and learned the theory nehind the loop filter and vco and stuff and implemented a model with system generator that operates @ 300 MHz and capable of tracking b-q-8-psk signals. I know its no big deal.

So i thought i could implement the timing recovery now with some work, but I couldn't. I have studied the papers, simulink models, reference hdl codes.

Ok, i am trying to implement the timing recovery circuit with gardner ted. I have the blocks all ready; gardner ted, loop filter, vco and all that but when put together they simply don't work. I even tried direct conversion of the matlab simulink demo to vhdl but i am missing something.

My gardner ted samples twice the symbol rate and outputs the correspoing error. I have my loop filter parameters (which i believe is not the cause of my problem). I implemented the vco with good sensitivity and correct center frequency.

Do you have any suggestions for me? Should i do more reading? Or did you have such experience?

Regards.

Your description is bit general.

There should be an analog VCO for timing recovery. What is it?

I am implementing all digital timing recovery, there should be no need for analog VCO.

You are through though, my description being too general. I will try to add some diagrams.

The way to debug a loop is to analyze each section for transfer function and look for symptoms of self-noise, offsets or errors of nonlinearity.

Using a high speed DAC to give TED output results for S curve analysis or eye patterns and may be useful. Also look at how Fref phase noise is multiplied in your timing loop.

You have to get the basic design working at high SNR before you can look at low SNR with MLTED detection and make improvements where needed. For example how much jitter in latency of processing critical sampling can be observed with a spectrum analyzer or scope with the loop open and look at the error signal beat pattern.

What capture range do you expect? Is it much wider than the initial error frequency?

@SunnySkyguy Thank you for your suggestion (analyzing each section for self-noise etc.). The problem is it doesn't even work in simulation so i know it won't work on the FPGAs.

I will post my blocks now.

Below is the gardner ted; Trig input comes from the vco at decided sampling points.



Below is the loop filter; kp and ki are easy to fiddle with.



Below is the simulink equivalent of my vco which i implemented in system generator. I cannot post the exact model since its not only my property. This block is followed by a "greater than zero comparator" to output pulses from the incoming vco.



These are the basic elements. Resampling circuit is simply a register enabled by the vco signal.

Below is my reference design from matlab.



I am feeding the gardner ted and resamplers with 2 samples per symbol. I do not employ any matched filtering. The above examples TED input looks similar to my real world signal.

@SunnySkyguy Regarding the capture range since the two radios are fpgas the timing difference comes from the boards osc. difference. There is not much difference. I got away with the timing with simpler digital algorithms before up until i hit the 80Msps (40 at I and 40 at Q arm) with no FEC.

The busses at the output of my DDC are 245MHz. 245/40 ~= 6 samples were fine before but past that previous algorithms ( open-loop algorithms ) start to fail or become too dangerous. I came to the point that before employing higher order modulations to increase data throughput, I have the solve the timing recovery with less samples per symbols.

Should I build a model with more oversampling and lower modulations and start from there? I tried that also to no success but I can go that road again.

Regards.