switching freq and bandwidth of dc-dc buck voltage mode

[wholx]

dc/dc compensation network

hi,

i am confused about the relation between the switching freq and the bandwidth of the overall feedback converter. i read in a doc that the bandwidth should be 3 times smaller that the switching freq, how is that?

i made a circuit and found the output voltage of the error opamp doesnt look like a constant value until i increase the switching freq to a much higher value. the original design is Fsw = 100KHz so i made the bandwidth as 33KHz with a phase margin = 75degree. finally i need a Fsw=5MHz to get the constant Verramp. anyone can tell me what happened to my design? did i mistaken the constraint to the bandwidth by the the switching freq?

Added after 1 hours 42 minutes:

i see that if we wanna reduce the output ripple, we can increase the output capacitance or the switching frequency. i wanna know if there is a max value of switching frequency that the converter can work on?

 

[VVV]

Well, seeing that a switching power supply is really a sampled-data system, the maximum bandwidth is limited to 1/2 the switching frequency (Nyquist's theorem).

However, in the real world, the bandwidth should be limited to about 1/4 to 1/5 of the switching frequency.
But that is not a rule. And this is just an upper limit, it does not HAVE to be that high. Bandwidth can be only a few kHz. You make the bandwidth just high enough to obtain the transient response you need, while ensuring stability under all conditions of input voltage output load and additional output capacitance, which can be added to the load.

The switching frequency can be increased without a theoretical limit, current designs run into the MHz range. What limits the switching frequency is speed of the transistors, the losses in the magnetics and windings and the difficulty to drive the transistors (capacitive load), which ultimately translate into higher losses. Also, do not forget the EMI issues, which can also paly a role in choosing the switching frequency.

 

[huojinsi]

VVV's explanation always make me more easy to understand doubt. I very admire
VVV for his knowledge!

 

[wholx]

thx VVV.
i came up with an idea that the output stage of the converter works like a lowpass filter which will block the high freq and then gets a dc output. is this right for the limit of the switching freq to bandwidth§

 

[rockycheng]

thx VVV.
i came up with an idea that the output stage of the converter works like a lowpass filter which will block the high freq and then gets a dc output. is this right for the limit of the switching freq to bandwidth§

I think this is only a fundamental requirement for switching frequency. The pole introduced by the low pass filter is much less than the bandwidth of converter, while the bandwidth is 1/4 to 1/5 times less than the switching frequency, as VVV said.

 

[wholx]

rockycheng,
u are right. i mistook the bandwidth of compensated converteur with the pole of output stage. i just wanted to give an intuitive view on the reason that the bandwidth Fbw is limited by the switching frequency Fs.

but did u guys ever read the following doc from TI? a part on page 8 where i've already highlighted says that the overall bandwidth has to be selected within the range Fs/10 < Fbw < Fs/3. we used the same compensation tech in the project i just finished. however the difference is our Fs is 100KHz and output capacitance and inductance is 10uF (with ESR = 10mohms) and 22uH relatively. to compensate the unstable converter, i put two zeros near the pole given by LC. in fact, i made a design of compensation network with an overall Fbw = 1MHz and phase margin of 40 degrees, but due to smaller Fs =100KHz, i had to reduce the Fbw to around 30KHz and ended up with a 75 degree phase margin. another constrain due to the parasitic capacitances limited the min value of capacitances in compensation and thus limited the max value of the resistor and thus the DC gain couldn't be achieved at a higher value.

just wanna share these with u. any comments are welcome.

 

[out to lunch]

technical brief on compensating voltage mode buck regulators...

**broken link removed**

 

[VVV]

Did you actually measure the gain-phase of your converter, or did you just calculate it? Quite often, what you measure is diffrerent, because of the parasitics that you do not accunt for. And just because the compensation has a BW of 1MHz, it does not mean that it actually does anything.
Perhaps you can share the values of the components (inductor, caps, ESR) and feedback components. I would like to take a look at them.

As for the DC gain being too small, I do not understand that. If you used the compensation network presented, then that has no DC path between the error amp output and its (-) input, so the DC gain should only be limited by the opamp, not the feedback.

 

[wholx]

you are right VVV, the DC gain is not influenced by the feedback network, but the compensation network's gain between its first zero and second zero equals the ratio of the two resistor in the feedback network. consequently, for higher frequency, it's like the feedback who plays the DC gain, as well as the DC gain of the opamp.