switched capacitor sample and hold circuit

[pseudockb]

holding capacitor sample and hold

Hi, I am designing a SC sample and hold circuit as shown in the following picture. When I used a large holding cap of 1pF, the output of the opamp takes a longer time to settle down at phase 1. Furthermore, the output during phase 2 seems to deviate more from the ideal sampled value. Could someone please explain to me? I have attached the simulation result for holding cap of 100f and 1pF. Thanks

 

[sunking]

capacitor sample

the PM of opa is too small

 

[philipwang]

Dear pseudockb,
1. As Sunking mentioned, your problem maybe comes from the lower phase margin of amp. ;
2. Advise to pay attention to the CMFB of the amp., you can adopt ideal CMFB and simulate the SC S/H circuit again to find whether the problem can be resolved.
Just try it!

Bg,

 

[princerock]

site:www.edaboard.com hold

Agree with sunking. check your phase margin first

 

[pseudockb]

Thank you all for the valueable inputs!!

Another question from me again.
From what I see, the capacitive load that the OTA sees during phase 1 is just the capacitive load(CL) at the output node while at phase 2, the OTA sees a load which is a parallel combination of the holding capacitor (CH) and the capacitive load. Supposing now that CH needs to be 5pF to meet the sampling noise requirement and CL is 100fF, it seems hard to design a OTA that has sufficient phase margin and gain bandwidth product at both load conditions. Is there an OTA architecture that has a phase margin independent of the load condition or any other way to solve this? Thanks a lot.

 

[faninglee]

if the offset of s/h circuit is very big, dc gain of OTA is a little small. at large,the gain is more 120DB.about you? at first PM(phase margin) of OTA must be sufficient.