Switched capacitor circuit

[crutschow]

Since you have no question mark, I see no question. But what you said above is true.

 

[mordak]

Stored voltage in switched capacitor circuits

Hey guys,

I have a basic question about SC circuits. Say we want to have a switched cap circuit as a sample and hold in an ADC or as an integrator. If the resolution of the converter is expected to be 10 bits, I wonder if it means that the voltage stored on the capacitor should be within one LSB error of the input signal (i.e if input is 1 volt and resolution is 10 bits (SNR=60dB), the stored voltage should be 1V +/- 1V/2^11) or not.

Thanks!


- - - Updated - - -

Since you have no question mark, I see no question. But what you said above is true.

Sorry I edited the post. So if it's like this, is it possible at all to have any switched cap circuit with 14 bit resolution?
It would be like less than 0.06mV error with 1volt full scale.

 

[crutschow]

It is possible but it requires careful design to minimize the charge injection from the CMOS gates into the signal path.

 

[mordak]

It is possible but it requires careful design to minimize the charge injection from the CMOS gates into the signal path.

I think it is impossible to have that much error for high speed applications, especially when cap size is not small. Becuase the resistance of the switch is not small (no matter how huge that switch is), so it would cause some difference between input and output. But I think that error would be treated as gain error of the whole ADC, and it will not affect the SNR value.