switch control signal question

Hello!

I am having an nmos switch, that i want it to shut off when my comparator gives "0". But i want it to keep on NOT conducting a bit more than the output of the comparator. So as you see in the attached pic, my idea is to delay the output of the comparator, and with an AND function to get a signal that gets 0 in the crucial moment, and stays there a bit longer....

QUESTIONS:
1-is there any other idea on how to keep the "0"=not conducting phase a bit longer?
2-(MORE IMPORTANT) can i implement somehow this function of an AND gate without the gate? so i don't have the delay of the gate? A more "hardware" solution? Something like a node where i could give my two signals (ouput and delayed version) and the AND function is inherited and happens instanteously?

Ok, it might be wishful thinking that something like that exists, but thank you in advance

PS happy easter to everyone honouring the day today

Could you attach another picture showing the desirable waveform you need ?

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there it is with more details, hope that's better

Here is one delayed pulse circuit
connect inverted comparator output to diodes cathode



Another way is , use CMOS inverters or schmitt-triggers and RC-delay

Regards KAK

hmmm i am doing everything in IC how can i use LM555 in an IC circuit? I was just thinking of simple cascaded inverters to add some delay... but still that's the least important. Any idea on how to create an AND gate function without the AND gate? nevertheless thank you

geozog86 said:

... Any idea on how to create an AND gate function without the AND gate?

Click to expand...

You could use an EXNOR gate, which might be a little bit faster. However, its falling edge output will still arrive later than your crucial falling edge comp output (not counting the delay in the switch itself).

Can you afford a further delay? Something in between the comp_output and the delayed_comp_output, name it -- say -- short_delayed_comp_output. So you could create your control_signal as shown above (using an AND or EXNOR gate), but let your switch work on the short_delayed_comp_output.

my issue is to avoid any temperature deviations...So i want to avoid the AND gate exactly for that. I have made the comparator to deliver a constant over temperature change of state (happening at time 0 let's say) but if this will be read after the AND gate at 0+5nsec in -10oC and 0+25nsec in +80oC then i won't like it That's why my ideal solution would be if i could just somehow exchange the accuracy on one slope with the accuracy on the other....so i get an instantaneous 0 and not good 1....The short_delayed version sounds ok, if it would be temperature independent....and i don't think it'll be

geozog86 said:

... i am doing everything in IC...

Click to expand...

If the system was designed in an ASIC enviroment maybe you must consider some syncronous based solution.

http://www.atmel.com/dyn/resources/prod_documents/doc1205.pdf

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