aminpix
Full Member level 2
I am trying to connect a two DDR3 to a Zynq FPGA. I need to swap some pins for DDR constrain purpose.
I had swap some data pins with some DDR_DMx pins as shown in the pictures.
DDR_DQxx are data pins and DDR_DMx are connected to DM pins.
The following pin connections are good or not?
I had swap some data pins with some DDR_DMx pins as shown in the pictures.
DDR_DQxx are data pins and DDR_DMx are connected to DM pins.
The following pin connections are good or not?