supply voltage and delay

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Suppose we design a ckt in tanner tool & simulate it in SPICE using particular technology. Now, if we operate the same ckt at lower Vdd, the propagation delay is more. Why this happens..?
 

@pavan garate: As supply voltage is reduced,the Power Delay Product of CMOS circuits decreases & delay increases.
Hence,while it is desirable to use the lowest possible supply voltage,in practice only as low a supply voltage can be used as corresponds to a delay that can be compensated by other means.

Circuit delay is inversely proportional to Vdd as first order of approximation.The increased delay can be overcome if device dimensions are also scaled down along with Vdd
 
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