supply sequencing in Low Power ASICs and On Board

[vcnvcc]

Before my question this is the assumption
- I am assuming Supply sequencing is same - within ASIC which has many power domains, and within ICs which are sitting on Board.

1. What is the need of supply sequencing within ASIC which has multiple power domains.
2. If we don't follow it what are the violations?
3. How to catch them during ASIC development?
3.a Which TOOL will catch it?

4. Very Imp for me - IF you have come across such situation - please share your valuable inputs..

Thank you..

 

[ThisIsNotSam]

first and foremost, the power sequence that matters the most is the one imposed by the IOs. Sometimes you have to turn the reference before the output stage source, sometimes order doesn't matter. But usually the order goes reference voltage (IO, something like 1.8V), output stage voltage (something like 2.5/3.3V), and then core (0.8/1V generally).

The multiple power domains internal to the chip are as complicated as you design them. Reset order matters, control signaling matters, etc. The worst case scenario would be a temporary glitch on some control signal that enables a power configuration that is not valid, drawing too much power or worse. Power related verification is the way to go, through simulation of power domain switching and through careful definition of the power mode constraints/intent. No tool will 'catch it' if you don't exercise it.