Supply capacitors

Two types or values are specified for several reasons:
1. sometimes to simplify the schematic, in reality they may be in different physical locations but still connected across each other.
2. Most likely in this case because different types of capacitor have different characteristics. I would guess the 1uF and 4.7uF in this schematic are expected to be electrolytic and 10nF/100nF expected to be ceramic. In general, the larger the value, especially in electrolytics, the poorer they are at high frequencies because of internal inductance and ESR. Ceramics are better at high frequencies but may be physically large when big values are needed. Using both types in parallel ensures they work at both low and high frequencies.

Brian.

betwixt said:

Two types or values are specified for several reasons:
1. sometimes to simplify the schematic, in reality they may be in different physical locations but still connected across each other.
2. Most likely in this case because different types of capacitor have different characteristics. I would guess the 1uF and 4.7uF in this schematic are expected to be electrolytic and 10nF/100nF expected to be ceramic. In general, the larger the value, especially in electrolytics, the poorer they are at high frequencies because of internal inductance and ESR. Ceramics are better at high frequencies but may be physically large when big values are needed. Using both types in parallel ensures they work at both low and high frequencies.

Brian.

Click to expand...

Thank you so much

betwixt said:

Two types or values are specified for several reasons:
1. sometimes to simplify the schematic, in reality they may be in different physical locations but still connected across each other.
2. Most likely in this case because different types of capacitor have different characteristics. I would guess the 1uF and 4.7uF in this schematic are expected to be electrolytic and 10nF/100nF expected to be ceramic. In general, the larger the value, especially in electrolytics, the poorer they are at high frequencies because of internal inductance and ESR. Ceramics are better at high frequencies but may be physically large when big values are needed. Using both types in parallel ensures they work at both low and high frequencies.

Brian.

Click to expand...

And what about the 5*100 nF + 1*4.7 uF ? should I use 5 capacitors of 100 nF and one capacitor of 4.7 uF? Because there are three pins in my model for VDD. So i don't understand

Wiring to the 4.7uF should be short but because it isn't much good at HF the wiring isn't critical. The other capacitors need short connections to the IC with one fitted close to each VDD pin, hence needing several. Keep the capacitor as close as possible between VSS and VDD (you have to connect all the VDD and VSS pins!) to keep the supply impedance low.

Brian.

betwixt said:

Wiring to the 4.7uF should be short but because it isn't much good at HF the wiring isn't critical. The other capacitors need short connections to the IC with one fitted close to each VDD pin, hence needing several. Keep the capacitor as close as possible between VSS and VDD (you have to connect all the VDD and VSS pins!) to keep the supply impedance low.

Brian.

Click to expand...

if connect to each VDD pin a 4.7 uF capacitor, where should i put the extra 100 nF capacitor ?

betwixt said:

Wiring to the 4.7uF should be short but because it isn't much good at HF the wiring isn't critical.

Click to expand...

I see it differently.

It says 5 x 100nF + 1 x 4u7
This means
* a 100nF very close at each VDD pin (here they assume 5 VDD pins per IC)
* plus a 4uF bulk capacitor somewhere a the PCB. (placement uncritical, since the high frequency is already blocked by the 100nF)

Klaus

KlausST said:

I see it differently.

It says 5 x 100nF + 1 x 4u7

Click to expand...

yeah right sorry

KlausST said:

This means
* a 100nF very close at each VDD pin (here they assume 5 VDD pins per IC)
* plus a 4uF bulk capacitor somewhere a the PCB. (placement uncritical, since the high frequency is already blocked by the 100nF)

Click to expand...

ok thank you

KlausST said:

Klaus

Click to expand...

These days, 1uF and 4.7uF are more likely MLCC (ceramic). Except for output capacitors of some linear voltage regulators that become unstable with ceramic capacitor load because they require a minimal ESR amount for stability.

There's a million choices here so duplicate the best layout recommendation with the Bill of Material (BOM) component size, e.g. 603 and placement.
Short answer , read more and copy the biggest or best solution in datasheets or uC kits or uC forums and ignore some DIY advice webpages unless the person understand what SRF and Q means and has measured it.

Here I expect <10 mohm ESR for ceramic and low ESR e-caps ESR*C < 10 us so 4 uF might be 2 ohms. Yet a standard e-cap will be 100 times bigger and useless. Sometimes too many low ESR caps causes resonance issues.

long answer (written hastily with out error checking)

A VLSI uC is a noise generator on Vdd with a few capacitors on each transistor that discharges on any clock transition. You supply noise depends depends on the output conductance vs f and load noise being attenuated by a smooth RLC filter.

Everything including wires, traces, capacitors, resistors, inductors and ICs each has an equivalent RLC value. yet schematics show ideal logical traces to mean ideal R=L=C=0. but this is not reality. We make it as small as possible to neglect. Even a short skinny trace of 1mm can be 1 nH which is ~ 1.5 Ohms is 10 times bigger and cannot attenuate a supply ripply from a 1% load error supply at 5V/1A = 50 mOhm supply generating 100 mV of SMPS ripple.

The uC IC is a million little FETs with capacitance that =charge and dump every transition. This can accumulate to a significant noise level, so we must choose caps that are 100 times bigger and much lower ESR> My paper napkin estimate of an STM32 is more than 1000 pF (1nF) of noise capacitance or more, which is also in the 1 ohm range at 150 MHz. So my using low ESR caps in that range the IC noice can be attenuated. Then for lower frequency noise, we add x uF e-Caps.

Keep in mind the bandwidth is related to the rise time of uC pulses, not just the repetition rate (CLK) f=0.35/ Tr So the noise injected by a uC can spread over 150 MHz with a 2ns rise time. This means we use an equivalent of Ohm's Law to attenuate noise at both ends which ends up being a complex low Q LPF filter design.

We consider the noise from both the source and the load by choosing caps over a wide spectrum so that the impedance at ESR*C is about 1% of the load noise source at the HF & VHF in the bands.

If all parts had ESR*C= T constant, then we would not have to consider parallel smaller parts. We would just assume like in e-caps, bigger C makes a smaller ESR, but in fact e-caps have alot of inductance in many layers inside the cap. So this bulk does not extend up into the VHF band that can be done by ceramic and plastic film.

Yet on schematics, we show C as just C but datasheets for an e-cap will have C, ESR and SRF where self-resonant frequency is due to path inductance (~0.7nH/mm typ. +/50% depending on length/width ratio) so e-caps have more effective series inductance(ESL) or simply L.

Consider schematics as logical wires but PCB traces as 7 nH/ cm and <1 to 4 pF/cm depending if there is a ground plane under the trace. Experts will estimate these and put them in their simulations with wide tolerances.

The rest of us just understand there is a good reason to use many caps to lower impedfance over a broad spectrum.

Wrap-up

In the 70's we didn't have simulation tools, so we just used 10 uF tantalum then ceramic 0.1 uF 1 nF and 100 pF NP0 in parallel ( unless it was simple analog) If we wanted to span from LF to UHF we chose from this standard then modified these guestimates as our understanding improved on impedance ratios and attenuation of noise sources and quality of passive components improved. But now with Digital VLSI the noise sources are much higher frequency so the deneral guidelines have changed. In TTL 1 cap per 10 IC's was fine. But for CMOS logic, every IC must have a cap, even if its only 1 nF for a simple IC. Because CMOS uses Enh-mode FETs and the lower the RdsON, the greater the Ciss Coss capacitance for input and output.

Low ESR ceramics are now replacing electrolytics and low ESR e-caps are also improving so they the choices are getting simpler.

This 4D nomograph is like a slide rule. You can solve for any RLCf variable with the intersection and compute Q and attenuation or gain.

Representative C ESR capability :








Regards, Dana.

This power distribution network may not mimic the RLC vales in your choices, but it tells me the electrolytic is too small to be useful other than to reduce the peak resonance of the ceramic caps with the 5mm to 1cm wire inductance of a twisted pair to the board.

1. How would you rank ABCD ?
2. What changes would you make in the simulation of each value of the STM32 and caps?
3. What PDN specs would you choose for attenuation vs freq.?
anyone?

STM model of Cout=10 pF/gate (swag) * N synchronous gates =?? Rs= 25 ohms/N

Best guess of average low ESR values of unknown C's suggested.

The reverse direction should also be tested. with another pair of DPDT's switch
simulation.

This tests s21 of the PDN. with far too many assumptions.