Suggest ADC with 1 us conversion time and 10 bit resolution

[opamp741]

suggest ADC architecture

I need to design an ADC with conversion time of 1 us and resolution of 10 bit..plz give ur suggestions about architecture??

 

[bastos4321]

Re: suggest ADC architecture

You can try do develop a SAR. For that frequency the clock will be 12-14MHz.

Bastos

 

[bear7679]

Re: suggest ADC architecture

You can also use pipeline ADC.

 

[djalli]

suggest ADC architecture

Try the worst in begining. Then move the fastest. 1us you are at Mhz resolution with 10bits in quatization which is not that fast. Remember that.

 

[hunan007]

Re: suggest ADC architecture

If the specifications of the ADC is 1MSPS+10bits,I think pipeline ADC or SAR is availalbe.

 

[konrad]

Re: suggest ADC architecture

At these specs a sigma-delta would be my selection

-Konrad

 

[watersky]

suggest ADC architecture

i think sar is a good idea for a beginner. the difficulty is the comp, which performance decides the parameter of your adc.

 

[opamp741]

Re: suggest ADC architecture

sorry to say but i didnt got the right response till now. everybody had its own answer but nobody given the logical reason behind that. Plz justify.

 

[watersky]

suggest ADC architecture

you can find speciality of each architecture from the book of ALLEN. you can choose one of them with your request. otherwise you must choose an architecture that you have some datum. the architecture of sar include: sampling,compare,logic, flip-latch of output. if your power supply of analog and digit is different,you need a levelshift. the technics you will use determine whether you can realize this architecture. if you are a beginner, this architecture is better. because its difficulty only is compare and its architecture is simpler than others.

 

[kyrandia]

Re: suggest ADC architecture

sorry to say but i didnt got the right response till now. everybody had its own answer but nobody given the logical reason behind that. Plz justify.

What are you looking for? Right response or the man who give you a right response? Well, I think SAR, pipeline and sd ADC all can full fill with your demand. But considering die size, power and complexity, I think SAR is the best solution.

 

[bastos4321]

Re: suggest ADC architecture

As I previous said, the SAR will be your best choise in therms of power, size and also complexity as also kyrandia mention. You can easy obtain the 10 bit matching from a capacitor array.

Bastos

 

[piao]

suggest ADC architecture

To a beginner, I think SAR is the first choice. you can also refer to "principle of data conversion" written by Razavi.

 

[opamp741]

Re: suggest ADC architecture

As suggested by most of u, I hav used Pipeliened architecture (2.5b/stage) for my ADC..Now I got few more doubts..i never seen anybody putting SOC(start of conversion pulse) and EOC(end of conversion pulse) in pipelined ADC..how to do that?..waiting for ur suggstions..
Regards

 

[zmliu]

Re: suggest ADC architecture

Sigma-delta or Pipeline.

 

[segabird]

Re: suggest ADC architecture

As suggested by most of u, I hav used Pipeliened architecture (2.5b/stage) for my ADC..Now I got few more doubts..i never seen anybody putting SOC(start of conversion pulse) and EOC(end of conversion pulse) in pipelined ADC..how to do that?..waiting for ur suggstions..
Regards

You can find the answer in the book "principle of data conversion" written by Razavi.

 

[piao]

suggest ADC architecture

sigma -delta is used in high resolution, and pipeline is used in high speed, so you just need to design a SAR. that's enough!

 

[codec]

Re: suggest ADC architecture

SAR is the best choice I think.
For higher speed, pipelined ADC is used.

 

[xuel]

Re: suggest ADC architecture

Yeah,SAR is the best choice I think. Because compared with SAR, it is a little difficuit to achieve 10bit for pipeline ADC.

 

[colonel]

Re: suggest ADC architecture

As suggested by most of u, I hav used Pipeliened architecture (2.5b/stage) for my ADC..Now I got few more doubts..i never seen anybody putting SOC(start of conversion pulse) and EOC(end of conversion pulse) in pipelined ADC..how to do that?..waiting for ur suggstions..
Regards

You can find the answer in the book "principle of data conversion" written by Razavi.

can I find this book on this site ?

 

[blue_orangee]

suggest ADC architecture

xuel wrote @Yeah,SAR is the best choice I think. Because compared with SAR, it is a little difficuit to achieve 10bit for pipeline ADC."
what does it mean?