Successive approximation register

[Mline7]

verilog code for sar

Hi,

I'm a pure analog designer, and I'm now facing my limits with digital issues. I have designed a complete 8 bit charge redistribution SAR ADC. I made up the sar (successive approximation register) by hand, i.e. by instanciating gates in schematic.

However, I'm looking for a smarter solution. I'd like to learn how to code the SAR in RTL.

Can someone help me out with some example of SAR RTL?

Thanks in advance

 

[nijMcnij]

successive approximation adc in vhdl

hello mline7

i have a very similar task of designing a 10 bit <1mW SAR ADC in AMS .35micro.

i did some reasearch and found out that the only possible was to meet the requirements is by using charge redistribution concept. however, i am new to the topic and don't know where and how to start.

can u please provide some references (paper, tutorials ...) or information as to how i can design such a thing.
i am completely in the dark here.

as to the SAR design, i think i can assist in that, but u have to clarify a bit how the SAR should behave exactly(i know what the thing basically does, but inorder to code verilog u have to define all the ports, inputs and outputs).

many thanks

 

[jcpu]

sar adc vhdl

Hello,

One more thought would bring up this:
What if the digital guy give us the Verilog / VHDL code,
what can we do about it?

 

[yeewong_su]

sar register in vhdl

No pure digtial code can do this ADC

 

[pixel]

sar circuit diagram

Digital logic for SAR is not so complex, and the best way is to do it by yourself with D-FF with asynchronous reset. You have such schematics in books. Only you need to adjust your start and stop signals. If somebody else writes vhdl code for you, you will need additional time. If you write as analog designer you will always suspect

 

[Syukri]

sar adc book

Hi ...

I'm now also making a project of SAR-ADC 8 bit

Well I'm responsible for the analog part....comparator, sample and hold and DAC.

For the SAR logic my partner is using verilog...then turn it to netlist

 

[jcpu]

+sar +adc +topology

Syukri wrote

Well I'm responsible for the analog part....comparator, sample and hold and DAC.

For the SAR logic my partner is using verilog...then turn it to netlist

Dear Syukri:

Please advise us, what happens next?
Should we turn everything into HSPICE and do the rest of simulation?

Thanks in advance,

 

[nijMcnij]

hot to build 8 bit sar adc

hello Syukri,

i am doing a 10bit SAR ADC also, but i am new to the field, can u please provide the reference names for the books and papers that u are using to design your SAR ADC.

many thanks for your help

 

[Syukri]

8 bit sar adc schematic

Hi all...

Generally speaking..al thing must be turn into netlist before it can be simulate but advancement in tools make it posible that the tools itself generate it for u.

Well in my SAR-ADC case...my partner can generate the netlist from verilog. there is some reason for this :

1. SAR and all ADC is considered as MIxed Signal System..coz there is an analogue part and digital part ( the SAR logic ). Analog Circuit need to done from scratch...either netlist or schematic entry...from circuit design to layout everything is manual, unless you have a library that has various type of device with various spec.

2. Simply becasue my analogue comparator, sample and hold and DAC is in netlist...so to integrate our part to become complete SAR-ADC everything must be in same format..in this case the netlist.

Added after 7 minutes:

As i always said..this is only for refference...copy on the design is prohibitted

 

[nijMcnij]

schematic of sar adc

the paper does not say a thing about die area or power consumption


how much is yours doing?..

 

[Syukri]

sar design

I'm a circuit designer...my task is to build a system using transistor schematic from the spec given...only from specification. The circuit is builded is up to me to use what topology for comparator , DAC and track and hold.

Then an ok design will be build the layout ...and tape out....

as long as the total power on the netlist level on simukation meet the spec...then its pass to IC Design people to build the floor planning and so on.

 

[anhtuan]

digital logic for sar design

hello Syukri,

i am doing a 10bit SAR ADC also, but i am new to the field, can u please provide the reference names for the books and papers that u are using to design your SAR ADC.

many thanks for your help

i am also doing adc 8bits,ijust have books about it but don't have topology. if u have,please sent it to me! thanks u

 

[nijMcnij]

non redundant sar

these papers contain the topology and the theory behind it

 

[KKramer2000]

complete sar circuit diagram

Hai Shukri ....
what tool does ur friend use ... i have problem with SAR LOGIC also... look impossible to design from the scratch ...

 

[vivekmanutd]

design of sar - adc with sample and hold

can anyone provide vhdl code for 3 bit sar-adc?

 

[fly6987]

verilog successive approximation adc

For me, the best solution for the logic part is to do it by yourself (not in vhdl). Because the most difficult thing will happen when you begin to draw the layout of the circuit. The better solution is to use charge redistribution concept which allows to build the most compact system. But we should pay attention to the nonlinearity of the system if we want to reach a high resolution.

 

[manish12]

vhdl code for 8 bit sar

use ADS for same , it provide interface between schematic level to vhdl code level

/ modelsim can be interface as well as matlab too.

the task will be easier .

guess ,
what happen in the big companies(chip manufacturer ) and around big mixed chip design

 

[Jim cage]

4 bit sar adc with diagram

Try to use the flash ADC and then we you will see what is the problem

 

[manish12]

3bit sar

if so , take only 4 bit , otherwise h/w will be so large !

 

[stocol]

sar verilog

Hello,

One more thought would bring up this:
What if the digital guy give us the Verilog / VHDL code,
what can we do about it?

if u generate SAR register by VHDL code, the digital circuit probably redundant.
i have seen some paper about nonredundant SAR circuitry