Subthreshold OTA Design

I have to design an OTA in subthreshold region as a part of a project .
The specifications are not very stringent , I am only concerned about low power dissipation around 100's of nW and supply voltage less than 1v.
I have searched literature and found that gm/id approach can be used to design low power circuits but I am unable to adjust w/l using gm/id method .
If anyone could through some light on this issue , I will be very much thankful.
The circuit of OTA is attached.

1. Decide on the current consumption vs. bandwidth needed
2. With the technology current of your process and the gm/Id value needed, calculate the W/L ratios.

If you need more info, read the corresponding books, e.g. Paul Jespers' book "The gm/ID Methodology, A Sizing Tool for Low-voltage Analog CMOS Circuits" or David M. Binkley's "Tradeoffs and Optimization in Analog CMOS Design".

First of all thanks for reply erikl
I have read Paul Jespers' book and I have got some idea about gm/id methodology .
If I talk about the attached OTA ,I know that from slew rate specification tail current can be found and so w/l of current source, similarly from gain bandwidth gm of input differential pair transistors can be calculated and so its w/l .
The main problem is arising in sizing of pmos of differential pair and output transistors .
If you can give idea about how to decide gm or gm/id ratio of pmos ,then it will be quite helpful for me.

Thanks

zulqar said:

If you can give idea about how to decide gm or gm/id ratio of pmos ,then it will be quite helpful for me.

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First show your design with the W/L ratios which you have calculated so far, and tell your process or its technology current.

First of all I have taken tail current as 200nA and gm/id for current source as 20 . From gm/id vs id/(w/l) curve w/l is coming out to be 0.5 . As far as input stage is concerned as current is 100nA in each branch , I have chosen gm/id as 25 which gives w/l as 2.5 . This condition also fulfills bandwidth requirement which is coming out to be around 2 Mhz (If mirror ratio is taken as 5).
Now I am stuck at this point , don't have idea how to proceed with sizing of output and pmos differential pair transistors.
I am attaching the curves used.

You didn't reveal your process nor its technology current; from your gm/id and current values I just can guess it's a 0.18 or 0.13µm process, so its µn/µp ratio will be about 3..4 . For the pmos transistors' ratio I'd try such a multiplication factor: w/l ≈ 8 .. 10 and play with this ratio as to get the right voltage (≈ half supply voltage) @ OUT.

zulqar, where can I find the circuit discription of that you are using?

Yes erikl I am using 0.18um process.
You mean to say that w/l for input pmos transistors should be 3-4 times that of nmos transistors?
what about output stage transistors?

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AMSA84
The circuit I am using can be easily found in literature as 'three current mirror OTA'.

zulqar said:

Yes erikl I am using 0.18um process.
You mean to say that w/l for input pmos transistors should be 3-4 times that of nmos transistors?
what about output stage transistors?

Click to expand...

For symetric response the gm of both nmos and pmos fets should be the same, so Wp/Wn should be equal to Kn/Kp, where Kn,p are the current gain factors of fets in your process. Of course in real life You need to made trade-off between current gain factor and intrinsic capacitances of both transistors - dependly to process it could be in range between 2 and 5.
From my modest experience the input pair should works in moderate inversion - if=1 or 10 (for modern process - refer to Sansen lecture on last ISCAS conference about designing in 20nm and beyond) and try to bias current mirrors in moderate/strong inversion - if in the range of 10-50.
if is of course the ratio of drain current over specific current. For better results include mobility degradation by lateral and vertical electric field.

zulqar said:

Yes erikl I am using 0.18um process.
You mean to say that w/l for input pmos transistors should be 3-4 times that of nmos transistors?

Click to expand...

Yes.

zulqar said:

what about output stage transistors?

Click to expand...

Same factor.

First of all thanks for reply Dominik
If I bias even current mirrors in subthreshold , then besides low power consumption will there be any other benefit as well?
Thanks

In weak inversion mosfets has a more headroom (Vdsat~3Vt) but much worse matching.