Hi
@Sameerpy
You are having a set of mistakes in layout, I have marked them on the screenshot attached.
1. M7a & M1a bulk should be connected to net N1 -> in your layout connected to vdd (all PMOS are in the same NWELL with same potential);
2. M7b & M1b bulk should be connected to net N1 -> in your layout connected to vdd ;
3. M5a bulk should be connected to net N3 -> in your layout connected to vss (all NMOS are in the same PSUB with same potential);
4. M5b bulk should be connected to net N4 -> in your layout connected to vss;
5. M4a bulk should be connected to net N5 -> in your layout connected to vdd;
6. M4b bulk should be connected to net N6 -> in your layout connected to vdd;
Please also note that your NMOS transistors M5a and M5b should be Deep NWELL devices, otherwise you cannot connect your substrate anywhere apart from vss (because it is sitting in the PSUB).
Since your circuit is quite simple, I can recommend modifying the schematic to get rid of unnecessary bulk connections so that all your PMOS bulks are VDD and all NMOS are VSS. In this case you wouldn't need to change anything in your layout and it should be fine.
If you would choose to change bulk connections as suggested, don't forget to re-simulate your circuit to make sure that the performance didn't change, or modify the circuit accordingly if it changed.
Hopefully, that helps.