Substrate connection error

[Sameerpy]

I got these error(mention below) while running DRC using divaRule of gpdk180nm. Here is attached Screenshots of layout and schematic. Devices are generated from source.

2 PSUB SUBVIA : Causes Multiple Stamped Connections.
1 PSUB SUBVIA : Has Multiple Stamped Connections.
3 Total errors found

 

[sidun.av]

Hi @Sameerpy
You are having a set of mistakes in layout, I have marked them on the screenshot attached.
1. M7a & M1a bulk should be connected to net N1 -> in your layout connected to vdd (all PMOS are in the same NWELL with same potential);
2. M7b & M1b bulk should be connected to net N1 -> in your layout connected to vdd ;
3. M5a bulk should be connected to net N3 -> in your layout connected to vss (all NMOS are in the same PSUB with same potential);
4. M5b bulk should be connected to net N4 -> in your layout connected to vss;
5. M4a bulk should be connected to net N5 -> in your layout connected to vdd;
6. M4b bulk should be connected to net N6 -> in your layout connected to vdd;

Please also note that your NMOS transistors M5a and M5b should be Deep NWELL devices, otherwise you cannot connect your substrate anywhere apart from vss (because it is sitting in the PSUB).
Since your circuit is quite simple, I can recommend modifying the schematic to get rid of unnecessary bulk connections so that all your PMOS bulks are VDD and all NMOS are VSS. In this case you wouldn't need to change anything in your layout and it should be fine.
If you would choose to change bulk connections as suggested, don't forget to re-simulate your circuit to make sure that the performance didn't change, or modify the circuit accordingly if it changed.

Hopefully, that helps.

 

[Sameerpy]

Hi @Sameerpy
You are having a set of mistakes in layout, I have marked them on the screenshot attached.
1. M7a & M1a bulk should be connected to net N1 -> in your layout connected to vdd (all PMOS are in the same NWELL with same potential);
2. M7b & M1b bulk should be connected to net N1 -> in your layout connected to vdd ;
3. M5a bulk should be connected to net N3 -> in your layout connected to vss (all NMOS are in the same PSUB with same potential);
4. M5b bulk should be connected to net N4 -> in your layout connected to vss;
5. M4a bulk should be connected to net N5 -> in your layout connected to vdd;
6. M4b bulk should be connected to net N6 -> in your layout connected to vdd;

Please also note that your NMOS transistors M5a and M5b should be Deep NWELL devices, otherwise you cannot connect your substrate anywhere apart from vss (because it is sitting in the PSUB).
Since your circuit is quite simple, I can recommend modifying the schematic to get rid of unnecessary bulk connections so that all your PMOS bulks are VDD and all NMOS are VSS. In this case you wouldn't need to change anything in your layout and it should be fine.
If you would choose to change bulk connections as suggested, don't forget to re-simulate your circuit to make sure that the performance didn't change, or modify the circuit accordingly if it changed.

Hopefully, that helps.

Hi @sidun.av
1. Actually in my layout I only make common nwell for M8a, M6a, M6b, M8a, M3a, M3b and make a nwell connection with VDD so body and source connected to VDD.
2. And for rest of PMOS I didn't make any common nwell and they are seperated from above mention PMOS.
3. M7b & M1b bulk are connected to net N1 (net 51) not VDD as you mention.
4. M5a bulk are connected to net N3 (net 52) not VSS as you mention.
Similarly other connections are also made such that their body and source connected together and both get connected to relevant net.

here are some screenshot

 

[sidun.av]

Actually in my layout I only make common nwell for M8a, M6a, M6b, M8a, M3a, M3b

My bad, it seems like I didn't look carefully at your layout. In any case, M5a and M5b NMOS devices are not Deep NWELL, so their bulk is not insulated from the common substrate, hence you cannot connect it to any other potential rather than VSS.
There are two possible solutions:
1. Replace M5a and M5b with Deep NWELL transistors;
2. Connect bulks of M5a and M5b to VSS.

 

[Sameerpy]

Hi , since I am working with gpdk180nm they didn't provide any device or template for deep nwell so I think it should be made manually but in layout also there is no DNW layer is showing for draw.
Can you help me regarding this.

 

[sidun.av]

Connect bulks of M5a and M5b to VSS.

Then this one is the only solution in your case.
If there are no DeepNWELL devices provided in the PDK, drawing the Deep NWELL layer wouldn't help, even if it is available for drawing. It simply means that this PDK doesn't support DeepNWELL feature.