sub-threshold transistor matching

Why transistors working in sub-threshold region has the matching problem.

in sub-threshold region, all the device parameter deviations influence the mismatch through exponential term, as opposed to quadratic term in saturation.

It is not true, matching of transistors in weak inversion is not influenced by ΔVth.
So in weak inversion transistor have better matching.

tyanata said:

It is not true, matching of transistors in weak inversion is not influenced by ΔVth.
So in weak inversion transistor have better matching.

Click to expand...

How do you mean - the matching is not influenced by ΔVth???
It is.

I found these words in Sansen's book on differential pair offset:

Pushing them into a weak inversion would make the offset voltage even smaller! Indeed for a weak inversion factor(VGT -Vt)/2 it can be substituted by nkT/q,which is always smaller than (VGT -Vt)

Thus in weak inversion it seems the matching is better.

I would recommend you to try to derive expression for offset, in order to understand how it functions.

A little help - mismatch/offset of differential pair, for example, is caused by several parameters (mismatch in Vth, K, W/L, load...). Some of them are dominant (Vth, W/L..).

Your citation from Sanson's book is probably taken out of a context, I recommend you to read it more carefully.

Once again, do the offset calculation manually and you'll see I'm right.

malizevzek said:

in sub-threshold region, all the device parameter deviations influence the mismatch through exponential term, as opposed to quadratic term in saturation.

Click to expand...

malizevzek, would the mismatch in VT in a differential pair for example result in a more pronouned effect on Id through the exponential term in sub-threshold region as opposed to quadratic term in saturation?

Therefore for same sized transistors the differential pair will match better in saturation than in sub-threshold.

Have I understood this correctly?

My result now is the voltage mismatch is better in weak inversion while the current mismatch is worse in weak inversion

For voltage mismatch you are right, why the current matching is worse?

I mean in a current mirror, the input voltage is the same, but since the mismatch now influence the gm in an exponential way, this makes the error bigger

fanshuo, you're basicaly right

I did a calculation, and the results say that for a differential pair with defined drain current, matching in weak inversion is better.
For the current mirror (with gate voltage defined) matching in weak inversion is worse.

So,
I have such a question.
If we have simple bias circuit: two NMOS, two PMOS, and rezistor between source of one of the NMOS and ground.
What is better NMOS to be in weak invesrion or in strong?

There is no single-valued answer. In the files the good example of the development of generator.

Hi, Loktik_Vitalij

may I asked you which book did you just consult?

"ANALOG DESIGN FOR CMOS VLSI SYSTEMS"
Franco Maloberti
Sufficiently intelligent book

tyanata said:

So,
I have such a question.
If we have simple bias circuit: two NMOS, two PMOS, and rezistor between source of one of the NMOS and ground.
What is better NMOS to be in weak invesrion or in strong?

Click to expand...

This depends upon your requirements, as there are trade-offs.

The PMOS almost definitely should be in strong inversion for best matching of current levels and reduced noise contribution. Using a long channel PMOS is good here, as it will push the device farther into strong inversion, improve the output resistance, reduce thermal noise and improve matching.

Since the bias is being used for biasing other circuits, the NMOS region of operation (subthreshold, moderate or strong inversion) could be on the top of the list. If you use a bias in one region of operation and circuits in the other, then the operation would be less consistent in those circuits over changes in operating condition (process, temperature)

If you have a low supply voltage, then you might desire subthreshold operation in the transistors to maintain low vdsat and vgs voltages.

Depending upon the tempco of your resistor, you might get best temperature performance with one region over another, due to changing temperature performance between subthreshold and strong inversion (and changing temperature performance within the strong inversion region)

It is unlikely, but you might even find that your best performance occurs when M2 is in strong inversion and M4 is in weak inversion.