You could also do the work quite simply by forcing two
subthreshold-range source currents a decade apart,
pick off the two Vgs values, a minus sign and badda-bing.
Now in real life on real silicon you'd want a real good
look at the qualities of that Id-Vg curve, because the
FinFET has several interfaces, all active to some extent
and you might see so much gate-kink weirdness (not
to mention all of the other non-classical behaviors)
that a single rollup subthreshold number has no useful
meaning, nor a good repeatable test method. Looking
to a model for that, is wishful not-thinking.