Sub Threshold problem while using TSMC 0.18 um technology

[elbadry]

Sub Threshold Problem

Dear All,

I am currently using TSMC 0.18 um technology. I suffer from the problem that for small currents ( few uA ), W/L has to be very small ( sometimes less than 1 ) to give reasonable Veff. Is there any way around that?

 

[Syukri]

Re: Sub Threshold Problem

YOu are using BSIM level 3 or 4?

Check the Vth value equation. Lower the Vth.

 

[mady79]

Re: Sub Threshold Problem

except current mirrors it's ok to operate input pair in subthreshold region as long as ur model supports .Mismatch would be more vgs-vt is low for current mirrors.

 

[elecomm]

Re: Sub Threshold Problem

Dear All,

I am currently using TSMC 0.18 um technology. I suffer from the problem that for small currents ( few uA ), W/L has to be very small ( sometimes less than 1 ) to give reasonable Veff. Is there any way around that?

I am asking what is the reasonable value for Veff ??? and why??is 50mV good or too little??

 

[mady79]

Re: Sub Threshold Problem

I really did not get what is the problem if W/L <1 .
Current mirrors try to have veff of 200 to 300mV ,see what your design permits ,but for others its fine to have lower vgst .
Dont get puzzled if you see -ve vgst ,thye operate in subthrehold .

 

[elbadry]

Re: Sub Threshold Problem

I really did not get what is the problem if W/L <1 .

The problem is that transistor matching would be unwieldy with W/L < 1 .Matched transistors need to be multiples of a unit transistor. Using W/L < 1 would force me to use a unit transistor with W/L < 1 which I think is area inefficient.

Does anyone know if TSMC accurately models the subthreshold region? How can I verify that the subthreshold regime is precisley modeled?


Thanks...

 

[elecomm]

Re: Sub Threshold Problem

I really did not get what is the problem if W/L <1 .
Current mirrors try to have veff of 200 to 300mV ,see what your design permits ,but for others its fine to have lower vgst .
Dont get puzzled if you see -ve vgst ,thye operate in subthrehold .

thnx...
1-why current mirrors need higher Veff??
2- does vgst=Vgs-Vth=Veff ???
3-is it normal to bias my devices with small values of Veff (~50mV)..for other devices not in the current mirror(while still having reasonable W/L)?

 

[Alles Gute]

Sub Threshold Problem

current mirrors need higher Veff becouse current mismatch will be higher if Veff is larger.
if you want low voltage mismatch, bias your transistor in weak inversion is better.

Normally, with Veff of 50 mV, your transistor will not be in strong inversion. A Veff value larger than 100mV is normally a safe value for strong inversion operation.